100AC Search Results

Contextual Info: Operating temperature Temperature rise Power dissipation at 70“C ambient Environmental classification Weight -55aC to + 100aC 30“C max. 0.8W 55/100/56 3.5g max. Note that Incremental Current is that current at which a 5% reduction in inductance occurs.

Contextual Info: Operating temperature 0.47-4.7pH -55aC to +125°C Operating temperature 5.6-390pH -55aC to +100aC 55aC max. 30aC max. 0.60W Temperature rise 0.47-4.7pH Temperature rise 5.6-390pH Power dissipation at 70'C ambiant 0.47-47pH Power dissipation at 70'C ambiant 5.6-390pH

Contextual Info: In su lated R.F. In d u cto rs sh ielded Operating temperature Temperature rise Power dissipation at W C ambient Environmental classification Weight Degree of coupling —55aC to +100aC 30aC max. 0.2W 55/100/21 l.Og max. 3% max. 30 min. 10.9 max. 30 min. _

CY7C1339

Contextual Info: fax id: 1109 PRELIMINARY CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1339 is a 3.3V 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

80486 microprocessor block diagram and pin diagram

Abstract: 64KX32 CY7C1336
Contextual Info: 36 PRELIMINARY CY7C1336 64K x 32 Synchronous Flow-Through 3.3V Cache RAM Features Functional Description • Supports 66-MHz microprocessor cache systems with zero wait states • 64K by 32 common I/O • Low Standby Power 1.65 mW, L version • Fast clock-to-output times

cy37128

Abstract: CY37128P160-125AC CY37128V CY7C375 CY37128P84-125JI cy3700
Contextual Info: = m m m !Æ '^ r ^ r : c Q CY3 7 1 2 8 PR £um A ^Y UltraLogic 128-Macrocell ISR™ CPLD — tco = 4.0 ns Features • • • • • • • • • • • 128 macrocells in eight logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming

LXXXXXXXX

Abstract: TNC 24 mk 2 026R CY7C09569V tb136 A14L CY7C09579V
Contextual Info: «oaHaoooiMMMWfMMMMMM!9:^ v’*'» -• -■ -■ -^ jjÉBT *¿f5’00“’ '*'^ 7“T ■ ■ ■ ■ <1; .r {• o CY7C09569V CY7C09579V PRELIMINARY f:,ò b 3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM • 3.3V Low o p e ratin g p ow er

RTL8201CL

Abstract: Realtek RTL8201CL RTL8201 rtl8201 fiber Realtek 8201 fiber 100base TXC10 realtek fiber rtl8201 application note AVDD33
Contextual Info: RTL8201CL REALTEK SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER RTL8201CL 7.3 Flow control support . 17 7.4 Hardware Configuration and Auto-negotiation. 17 7.5 LED and PHY Address Configuration . 18

SPRU099

Abstract: SPRU103 TMS320 mp 1009e SPRU099A
Contextual Info: TMS320C5xx C Source Debugger User’s Guide 1994 Microprocessor Development Systems Printed in U.S.A., June 1994, reprinted October 1997 SDS SPRU099A TMS320C5xx C Source Debugger 1994 User’s Guide TMS320C5xx C Source Debugger User’s Guide SPRU099 June 1994

SWS-L

Abstract: SWS600L-12 Nemic-Lambda users Nemic-Lambda tog cnt AWG 24 UL1007 SWS1000L 8486A SWS600L-24 S8B-PHDSS Nemic-Lambda power supply unit
Contextual Info: SWS-L Series Compact and high-power AC/DC power supply ・All specifications are subject to change without notice. Low Profile Low Fan Noise The SWS-L series is designed to have a lower profile than previous models. With the thin of 61mm, a 50% size reduction, these can be

Contextual Info: UltraLogic 128-Macrocell Flash CPLD is designed to bring th e ease o f use and high perform ance o f th e 22V10 to highdensity CPLDs. Features • 128 macrocells in eight logic blocks • 64 I/O pins T he 128 m acrocells in th e CY7C374 are di­ vided betw een eight logic blocks. Each

Contextual Info: RTL8201CL+ SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER DATASHEET Rev. 1.1 27 August 2003 Track ID: JATR-1076-21 RTL8201CL+ Datasheet COPYRIGHT 2003 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any

RTL8201 reference Design

Abstract: RTL8201bl reference Design
Contextual Info: RTL8201CL SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER DATASHEET Rev. 1.2 20 January 2004 Track ID: JATR-1076-21 RTL8201CL Datasheet COPYRIGHT 2004 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any

Contextual Info: UltraLogic 64-Macrocell Flash CPLD Features Functional Description • 64 m acrocells in four logic blocks T h e CY7C373 is a Flash erasable Com plex Program m able Logic Device C PL D and is p a rt o f th e F lash 370 ” family o f highdensity, high-speed C PLD s. Like all m em ­

15tb60

Abstract: L250J hfa15tb60
Contextual Info: PD -2.334 International l O R Rectifier HEXFRED H F A 15T B 60 Ultrafast, Soft Recovery Diode Features • • • • • • VR = 600V Ultrafast Recovery Ultrasoft Recovery Very Low lRRM Very LowQrr Guaranteed Avalanche Specified at Operating Conditions

tlp 453

Contextual Info: fax id: 6151 PRELIMINARY Ultra37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 10 ns Features — tS = 5.5 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — 3.3V ISR • • • • • • • • • — 5V tolerant

Contextual Info: HARRIS SEMICOND SECTOR 37E D 4305271 0021407 ñ • H A S 01E 13593 3875081 G E SOLID STATE TCD4030A Types CMOS Quad Exclusive-OR Gate B -i “ -»ta ¡Î-H A— “ ^ The R CA-C D 4030A types consist o f fo u r in­ dependent Exclusive-OR gates integrated on

allocator

Contextual Info: CY7C373Ì PRELIMINARY UltraLogic 64-Macrocell Flash CPLD Features Device CPLD and is part of the FLASH370i™ family of high-density, high­ speed CPLDs. Like all members of the F lash 37(H family, the CY7C373i is de­ signed to bring the ease of use and high

L133A

Contextual Info: CY7C1346 64K X 36 Synchronous-Pipelined Cache RAM Features The C Y 7 C 1 346 I/O pins can op era te at eith er the 2.5V o r the 3.3V level; the I/O pins are 3.3 V to le ra n t w h en V DDQ=2.5V. • Supports 10O-MHz bus for Pentium and PowerPC operations with zero wait states

SB520S

Contextual Info: SB520 - SB5100 5.0A SCHOTTKY BARRIER RECTIFIER Features Epitaxial Construction Guard Ring Die Construction for Transient Protection Low Power Loss, High Efficiency High Surge Capability High Current Capability and Low Forward Voltage Drop Surge Overload Rating to 150A Peak

IP101

Abstract: IP101 Lqfp48 R04 SMD duplex display IC PLUS 10BT AVDD33 smd ic 611 LM1117 16 PIN duplex led display
Contextual Info: IP101 Preliminary Data Sheet Single port 10/100 Fast Ethernet Transceiver Features General Description 10/100Mbps TX/FX Full-duplex or half-duplex Supports Auto MDI/MDIX function Fully compliant with IEEE 802.3/802.3u Supports IEEE 802.3u auto-negotiation

SL23

Abstract: SL24 SSL22 SSL23 SSL24
Contextual Info: E SSL22 • SSL24 TAIWAN SEMICONDUCTOR 2 .0 AMP. Surface M ount Low V f Schottky Barrier Rectifiers RoHS COMPLIANCE SMB/D 0-214A A . J Ï t l .ECi a Features -4-4- Fur s u rreco m ounted ap pi ication M e tal s lllcon Ju nctlori. ma]o rlty ca rrlor conduction

EAKD

Abstract: BUW12A
Contextual Info: MOTOROLA SC XSTRS/R F 1HE D I I b3b?2S4 QüôM'iai 1 I MOTOROLA SE M IC O N D U C T O R TECHNICAL DATA BUW 11,A BUW 12,A Designer's Data Sheet N P N Silicon Pow er Transistors Switchm ode Series These transistors are designed for high-voltage, high-speed, power switching in induc­

CY7C1345

Contextual Info: 345 CY7C1345 128K x 36 Synchronous Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 36 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wrap-around counter supporting either