01FL5 Search Results

Contextual Info: in te i, 83C51 KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER Direct Drive LED Outputs — Four Pins P3.7:4 — 13 mA Typical Current Sink Capability 20 pF Cap On-chip for RC Resonator — Frequency Selectable (4-6 MHz) • 128-byte On-chip RAM Memory ■ Clock/Data Drivers to Motherboard

Contextual Info: Data Sheet No. PD-6.013A International [ml Rectifier HIGH VOLTAGE IR 2 TIO L MOS GATE DRIVER General Description Features The IR2110L is a high voltage, high speed MOSgated power device driver with independent high side and low side referenced output channels. Proprietary

Contextual Info: SOLID STATE DEVICES INC 1SE D |fl3bb011 Ü0G1ÔS5 b | T - 03-11 SDR900 THRU SDR905 30 AMPS ULTRA FAST RECOVERY RECTIFIER 5 0 -5 0 0 VOLTS C A S E STYLE J DO-5 14830 Valley View Avenue La Mirada, California 90638 (213) 921-9660 TW X 910-583-4807 FAX 213-921-2396

TTK SG 2368

Abstract: BV EI 303 3628 7 segment LD 1106 BS LM 6863 D I8253 yx 8018 0308 082c ez 422 BV EI 304 3083 0429 01 2701 00 RELE 12,8 mhz e 4895 lf
Contextual Info: AP-55A APPLICATION NOTE i n t e i A u g u s t 1979 S.A. Distributor E l e c t r o n ic \ \ B u il d in g E l e m e n t s p t y l t d PURVEYORS OF a l l ELECTRONIC COMWNENTS Tel eph on e 7 8 - 9 2 2 1 / 6 P O B o x 4 6 0 9 , Pretoria T e l e x 3 01 8 1 S A

Contextual Info: ADVANCE INFORMATION in te i 83C196LC, 83C196LD CHMOS 16-BIT MICROCONTROLLER Automotive • 22 MHz operation High-speed event processor array — Six capture/compare channels ■ 32 Kbytes of on-chip ROM LC 16 Kbytes of on-chip ROM (LD) — Two compare-only channels

Contextual Info: 80960H A/H D/HT in te i 1.0 ABOUT THIS DOCUMENT This document describes the parametric perfor­ mance of Intel’s 80960Hx embedded superscalar microprocessors. Detailed descriptions for functional topics — other than parametric performance — are published in the i9 6 P H x M icroprocessor User’s

Contextual Info: in te i 28F020 2048K 256K x 8 CMOS FLASH MEMORY Flash Electrical Chip-Erase — 2 Second Typical Chip-Erase Quick-Pulse Programming Algorithm — 10 jLis Typical Byte-Program — 4 Second Chip-Program 100,000 Erase/Program Cycles 12.0V ± 5 % Vpp • Command Register Architecture for