83C196LC Search Results

A3233

Abstract: A3233-02
Contextual Info: intei ADVANCE INFORMATION 83C196LC, 83C196LD CHMOS 16-BIT MICROCONTROLLER Automotive • 22 MHz operation High-speed event processor array — Six capture/compare channels ■ 32 Kbytes of on-chip ROM LC 16 Kbytes of on-chip ROM (LD) — Two compare-only channels

8096 microcontroller

Abstract: 8096 microcontroller architecture application 8096 microcontroller datasheet MCS-96 architecture overview AD148 can bus automotive intel 8096 instruction set 16 bit 8096 microcontroller interrupt temperature controller using 8096 8096 microcontroller features
Contextual Info: PRODUCT PREVIEW 83C196LC, 83C196LD CHMOS 16-BIT MICROCONTROLLER Automotive • 22 MHz operation† ■ 32 Kbytes of on-chip ROM LC 16 Kbytes of on-chip ROM (LD) ■ 1 Kbyte of on-chip register RAM (LC) 384 bytes of on-chip register RAM (LD) ■ 512 bytes of on-chip code RAM

Contextual Info: ADVANCE INFORMATION in te i 83C196LC, 83C196LD CHMOS 16-BIT MICROCONTROLLER Automotive • 22 MHz operation High-speed event processor array — Six capture/compare channels ■ 32 Kbytes of on-chip ROM LC 16 Kbytes of on-chip ROM (LD) — Two compare-only channels

16 bit 8096 microcontroller architecture

Abstract: intel 8096 instruction set 8096 microcontroller features temperature controller using 8096 87C196JT AD14 83C196LC 83C196LD 87C196JR intel 8096
Contextual Info: ADVANCE INFORMATION 83C196LC, 83C196LD CHMOS 16-BIT MICROCONTROLLER Automotive • 22 MHz operation † ■ High-speed event processor array — Six capture/compare channels ■ 32 Kbytes of on-chip ROM LC 16 Kbytes of on-chip ROM (LD) — Two compare-only channels

87C196JR

Contextual Info: PRODUCT PREWEW intei 83C196LC, 83C196LD CHMOS 16-BIT M ICRO CO NTRO LLER Automotive • 22 M H z o p e ra t io n ^ H ig h-s pe e d e v ent p ro ce s s o r array ■ 32 K b y t e s o f o n - c h i p R O M L C 16 K b y t e s o f o n - c h i p R O M ( L D )

83C196LC

Abstract: 83C196LD 87C196JR 87C196JT AD12 AD14 intel Automotive
Contextual Info: ADVANCE INFORMATION 83C196LC, 83C196LD CHMOS 16-BIT MICROCONTROLLER Automotive • 22 MHz operation ■ 32 Kbytes of on-chip ROM LC 16 Kbytes of on-chip ROM (LD) ■ 1 Kbyte of on-chip register RAM (LC) 384 bytes of on-chip register RAM (LD) ■ 512 bytes of on-chip code RAM

Contextual Info: ADVANCE INFORMATION 83C196LD CHMOS 16-BIT MICROCONTROLLER Automotive • 22 MHz operation1 ■ Programmable 8- or 16-bit external bus ■ 16 Kbytes of on-chip ROM ■ Design enhancem ents for EMI reduction ■ 384 bytes of on-chip register RAM ■ Register-to-register architecture

8096 MICROCONTROLLER ADDRESSING MODES

Abstract: 8096 microcontroller block diagram 83C196LD 87C196JR AD11 AD12 AD14 272805 CCR-02 8096 microcontroller serial ports
Contextual Info: ADVANCE INFORMATION 83C196LD CHMOS 16-BIT MICROCONTROLLER Automotive • 22 MHz operation† ■ 16 Kbytes of on-chip ROM ■ 384 bytes of on-chip register RAM ■ Register-to-register architecture ■ Peripheral transaction server PTS with high-speed, microcoded interrupt

Contextual Info: ADVANCE INFORMATION 8 3 C 1 98 L D CHMOS 16-BIT MICROCONTROLLER Automotive • 22 MHz operation1 ■ Programmable 8- or 16-bit external bus ■ 16 Kbytes of on-chip ROM ■ Design enhancem ents for EMI reduction ■ 384 bytes of on-chip register RAM ■ Register-to-register architecture

87C196CA

Abstract: 1C20h j1850 protocol 87C196LA 8XC196Jx 8XC196KR a5264 IFR 6000 83C196LC 83C196LD
Contextual Info: 27297301.qxd 12/17/96 1:42 PM Page 1 8XC196Lx Supplement to 8XC196Kx, 8XC196Jx, 87C196CA User’s Manual 8XC196Lx Supplement to 8XC196Kx, 8XC196Jx, 87C196CA User’s Manual December 1996 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of

AD14

Abstract: 83C196LD 87C196JR AD10 AD11 AD12 272805
Contextual Info: ADVANCE INFORMATION 83C196LD CHMOS 16-bit Microcontroller Automotive J 22 MHz operation† J J 16 Kbytes of on-chip ROM J J 384 bytes of on-chip register RAM J Register-to-register architecture J Peripheral transaction server PTS with high-speed, microcoded interrupt