0013FLL Search Results

Contextual Info: « LOW-POWER HEX PECL-TO-TTL TRANSLATOR SYNERGY SEMICONDUCTOR FE A T U R E S PRELIMINARY SY100S390 DESCRIPTION The SY100S390 is a hex PECL-to-TTL translator for converting 100K logic levels to TTL logic levels. Unlike other level translators, the SY100S390 operates using only one

SY100S811

Contextual Info: This Material Copyrighted By Its Respective Manufacturer CiockWorks PRELIMINARY SY100S811 SYNE R Q Y SEMICONDUCTOR B L O C K D IA G R A M P E C L D C E L E C T R IC A L C H A R A C T E R IS T IC S Vcc = Vcco = 5.0V + 5% Ta = 0°C Symbol V bb Parameter Min.

SY100H841

Abstract: SY100H841ZC SY10H841 SY10H841ZC
Contextual Info: SINGLE SUPPLY PECL-TTL 1:4 CLOCK DRIVER SYNERGY SEMICONDUCTOR FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100H841 DESCRIPTION Translates positive ECL to TTL PECL-TTL 300ps pin-to-pin skew Guaranteed skew spec Differential internal design for Increased noise

Contextual Info: V PRELIMINARY SY10ELT22L SY100ELT22L d u a l t t l -t o - d if f e r e n t ia l SYNERGY p e c l tr a n s la to r SEMICONDUCTOR DESCRIPTION FEATURES The SY10ELT/100ELT22L are dual TTL-to-differential PECL translators. Because PECL Positive ECL levels are used, only +3.3V and ground are required. The small

Contextual Info: V _ _ 1:2 DIFFERENTIAL FANOUT BUFFER SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • 3.3V power supply The SY10EL7100EL11 are 1 :2 differential fanout gates. These devices are functionally similar to the E111 devices, with higher performance capabilities. Having

d400 e

Abstract: HLMP-3500 D400 GL 3401 104001 HLMP-D400 D401 HLMP-3300 HLMP-3400 HLMP-3762
Contextual Info: W h n l HEW LETT W lH Æ P A C K A R D T -l3/4 5 mm D iffused LED Lamps HLMP-3300 Series HLMP-3400 Series HLMP-3500 Series HLMP-3762 HLMP-3862 HLMP-3962 HLMP-D400 Series HLMP-D600 Technical Data Features • Reliable and Rugged • Available on Tape and R eel

TLA100-3E

Abstract: L0323-A twisted pair cable TWISTED PAIR WIRE PE64503 T7220 aui isolation transformer PE-64503 LAX-ET304 T7220A-PC
Contextual Info: Advance Data Sheet ^ a t &t r Microelectronics T7220A Twisted-Pair Medium Attachment Unit TPMAU2 Issue 0.2 Features Description • Compliance with IEEE 802.3 standards* for AUIinterface The T7220A Twisted-Pair Medium Attachment Unit (TPMAU2) simplifies the design and implementation

Contextual Info: * QUAD MULTIPLEXER/ LATCH SYNERGY SEMICONDUCTOR FEATURES SY100S355 DESCRIPTION • Max. propagation delay of 1100ps ■ Max. enable to output delay of I400ps ■ I ee min. of -80m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option:

Contextual Info: O • ira ENHANCED 4-STAGE COUNTER/SHIFT REGISTER ^ SYNERGY cvm n^A oYi 00S336A SEMICONDUCTOR FEATURES DESCRIPTION ■ Max. shift frequency of 700MHz ■ Clock to Q delay max. of 110Ops ■ Sn to TC speed improved by 50% ■ Sn set-up and hold tim e reduced by more than 50%

SY100EL05

Contextual Info: *SYNERGY PRELIMINARY SY10EL05 SY100EL05 2-INPUT DIFFERENTIAL AND/NAND SEMICONDUCTOR DESCRIPTION FEATURES 275ps propagation delay High bandwidth output transitions Internal 75K£2 input pull-down resistors ESD protection of 2000V The SY10EL7100EL05 are 2-input differential AND/NAND

Mlt-3

Abstract: Pin-for-Pin Compatible with the
Contextual Info: * PRELIMINARY SY67671 TP-PMD TRANSCEIVER SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • Adaptive Equalizer with Line Compensation Loop Control ■ On-board translation from NRZI to MLT-3 and vice-versa ■ Transmitter output disable option for quiet line ■ Supports up to 100 meters of Shielded Twisted Pair

PIC16C51

Contextual Info: PIC16C5X M ic r o c h ip EPROM/ROM-Based 8-Bit CMOS Microcontroller Series Pin Diagrams Devices Included in this Data Sheet • PIC16C54 PDIP, SOIC, Windowed CERDIP • P IC 16 C R 5 4 ^ ►RA1 Æ- • PIC16C55 RA2-«- > • PIC16C56 RA3-«- >

Contextual Info: « SYNERGY 8-BIT SCANNABLE R e g is t e r s^ 4 i SEMICONDUCTOR FEATURES DESCRIPTION • 1000ps max. CLK to output ■ Extended 100E V ee range of -4.2V to -5.5V ■ SHIFT overrides HOLD/LOAD control ■ Asynchronous Master Reset ■ Pin-compatible with E141

SY100E157

Abstract: SY10E157 SY10E157JC
Contextual Info: * SYNERGY QUAD 2:1 MULTIPLEXER SY10E157 SY100E157 SEMICONDUCTOR FEATURES DESCRIPTION Individual select controls The S Y 10/100E157 contain fo u r 2:1 m ultiplexers with differential outputs. The output data are controlled by the individual S elect SEL inputs. The individual select