XYXXX Search Results

KM428C257

Abstract: XAL W6 MAS 10 RCD sc 4145 CNR 14 V 471 K CA278 CI008 On Screen Display Samsung
Contextual Info: SA M S U N G E L E C T R O N I C S INC b7E D m 7^4142 001L>bb2 17Û SMGK PRELIMINARY KM428C257 CMOS VIDEO RAM 256K X 8 Bit CMOS Video RAM FEATURES GENERAL DESCRIPTION - Dual port Architecture 2 56 K x 8 bits RAM port 512 x 8 bits SAM port The Sam sung KM 428C 257 is a C M OS 256K x 8 bit Dual

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024x36x2 Integrated Device Technology, Inc. PRELIMINARY IDT72V3624 IDT72V3634 IDT72V3644 • M aster R eset clears d ata and configures FIFO, Partial R eset clears data but retains configuration settings

Contextual Info: | CMOS Bus-Matching SyncFlFO 256 x 36, 512 x 36,1,024 x 36 dt PRELIMINARY ¡DT723633 IDT723643 Integrated D ev ic e Techno logy, Inc. NOTE: There is an errata notice on the last page and the corrections have been incorporated into this document. FEATURES:

Contextual Info: In te g ra te d D e v i e T e d h n o Jo g y , lie . CMOS Triple Bus SyncFlFO1 With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 PRELIMINARY IDT723626 IDT723636 IDT723646 NOTE: There are two errata notices at the end of this data sheet. The May 20 errata describes corrections that have

Contextual Info: CY7B180 CY7B181 s CYPRESS SEMICONDUCTOR 4K x 18 Cache Tag Features • Can be used as 4K x 18 SRAM • Supports 66-MHz cache for all major high-speed processors Functional Description T he CY7B180 and CY7B181 are high-perform ance B iC M O S cache tag R A M s orga­

Contextual Info: CY7C43626 CY7C43636/CY7C43646 CY7C43666/CY7C43686 . PRELIMINARY 2 5 6 / 5 1 2 / 1 K /4 K / 1 6 K x 3 6 / x 1 8 x 2 T ri B u s F I F O Fully asynchronous and sim ultaneous read and write operation permitted Mailbox bypass register for each FIFO Parallel and Serial Programmable Almost-Full and Alm ost-Em pty flags

diode E1110

Abstract: lN4002 LN4003 ANA 618 20010 TDB 0123 km b3170 E1110 Diode UB8560D MAA723 moc 2030
Contextual Info: elektronik-bauelem ente I WT VD AVL 1 /8 7 Bl. 2 E r l ä u t e r u n g e n z u m I n h a l t und zu d e n A n g a b e n d e r B a u e l e m e n t e - V e r g l e i c h s l i s t e D ie B a u e l e m e n t e - V e r g l e i c h s l i s t e e n t h ä l t a l l e in d e r B i l a n z v e r a n t w o r t u n g d e s V E B K o m b i n a t

CHN 044 VW

Abstract: NB18
Contextual Info: CMOS SyncBiFIFO with Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 IDT723624 IDT723634 IDT723644 • Port B bus sizing ot 36-bits long word , 18-bits (word) and 9-bits (byte) • Big- or Little-Endian tormat tor word and byte bus sizes • Master Reset clears data and contigures FIFO, Partial

aexxxx

Contextual Info: fax id: 5219 :/ CYPRESS CY7C09349 CY7C09359 4K/8K x 18 Synchronous Dual-Port Static RAM • High-speed clock to data access 6.5/7.5/12 ns max. • Low operating power Features • True Dual-Ported m em ory cells which allow simu Itaneous access of the same memory location

SIT9002A

Abstract: SIT9002
Contextual Info: SiT9002 LVPECL / HCSL / LVDS / CML 1 to 800 MHz High Performance Spread Spectrum Oscillator Features Benefits • World’s first differential spread spectrum oscillator • Extremely low cycle-cycle jitter • As low as10 ps typical • Wide frequency range

Contextual Info: CY7B180 CY7B181 I CYPRESS SEMICONDUCTOR 4K x 18 Cache Tag Features • C an be used as 4K x 18 SRAM • Supports 66-MHz cache for all major high-speed processors • 4K x 18 tag organization • BiCMOS for optimum speed/power • High speed — 10-ns match delay

STA 518A

Contextual Info: M O TO R O LA SEMICONDUCTOR TECHNICAL DATA Product Preview MCM67B518A 32K x 18 Bit BurstRAM Synchronous Fast Static RAM With Burst Counter and Self-Timed Write T h e M C M 67B 518A is a 589,824 bit synchronous fa st static random a ccess m e m ory designed to provide a burstable, h ig h -p erform a n ce, secondary cache

TLP2200

Contextual Info: TO SHIBA TLP2200 TOSHIBA PHOTOCOUPLER GaA€As IRED & PHOTO-IC TLP220Q ISOLATED BUSS DRIVER Unit in mm HIGH SPEED LINE RECEIVER MICROPOCESSOR SYSTEM INTERFACES 8 DIRECT REPLACEMENT FOR HCPL-220Ö • Ip = 1.6mA Input Current Power Supply Voltage V c c = 4.5~20V

Contextual Info: BiCMOS SyncBiFIFO 64 x 36 x 2 IDT723612 J d t Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs (64 x 36 storage

EL B17

Contextual Info: CMOS Clocked FIFO With Bus-Matching and Byte Swapping IDT723613 6 4 x 3 6 I r t e g í a t e d D e v i e T e c h n o lo g y , l i e . FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge

b17b

Contextual Info: 3.3 VOLT CMOS SyncFIFO WITH BUS-MATCHING 256 x 36, 512 x 36,1,024 x 36 FEATURES: • Memory storage capacity: IDT72V3623-256 x 36 IDT72V3633-512 x 36 IDT72V3643-1,024 x 36 • Clock frequencies up to 67 MHz 10 ns access time • Clocked FIFO buffering data from Port A to Port B

B27E

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 PRELIMINARY IDT72V3614 Integrated Device Technology, Inc. FEATURES: • T w o independent clocked FIFOs 64 x 36 storage capacity each buffering data in opposite directions • Supports clock frequencies up to 67 MHz

26801B

Contextual Info: CMOS SyncFIFO 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 I DT 72 420 I DT 72 200 IDT7221 0 I DT 72 220 I DT 72 230 I DT 72 240 FEATURES: DESCRIPTION: • 6 4 x 8 -b it o rg a n iza tio n ID T 7 2 4 2 0 • 256 x 8 -b it o rg a n iz a tio n (ID T 7 2 2 0 0 )

Contextual Info: CY7C43646V CY7C43666V/CY7C43686V PRELIMINARY 3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO Features Fully a s y n c h ro n o u s and sim u lta n e o u s read and w rite o p e ratio n p erm itted • 3.3 V h ig h -sp eed , low -pow er, first-in first-o u t F IF O

dsa 362

Contextual Info: ADE-203-231B Z HM538123B Series 131072-word x 8-bit Multiport CMOS Video RAM H I T A The HM538123B is a 1-Mbit multiport video R A M equipped with a 128-kword x 8-bit dynamic C H I data between R A M and SAM . In addition, it has two modes to realize fast writing in RAM . Block

JXXX

Contextual Info: MITSUBISHI LSIs e MH64S72QJA -7,-8 e°- 4,831,838,208-BIT 67,108,864-WQRD BY 72-BIT Synchronous DYNAMIC RAM PRELIMINARY S o m e o f c o n te n ts are s u b je c t to c h a n g e w ith o u t n o tice . DESCRIPTION The MH64S72QJA is 67108864 - word x 72-bit

CT1602

Abstract: CT10894 54LS241 CT10897 bc 1602 l vector word CT1602FP 54LS244 54LS245 54LS32
Contextual Info: CTI MIL-STD-1553B REMOTE TERMINAL OR BUS CONTROLLER HYBRIDS march 1984 FEATURES GENERAL DESCRIPTION u The CT1602/CT1610 design incorporates five LSI chips that accomplish the dual redundant MIL-STD1553B Remote Terminal and/or Bus Controller Protocol Functions. Buffering has been added to the most com­

MAX-MFT

Abstract: T1IS DIN 46231 QQG1040
Contextual Info: ELECTRONIC DESIGNS INC SIE D m 3230114 Ü001040 347 H E L D ^ EDI Electronic DMfgm inc.* EDI8F2464C High Speed 1.5 Megabit SRAM Module 64Kx24 Static RAM CMOS, High Speed Module P B iU lO M Â B V T -V S t - 2 3 - / V Features The EDI8F2464C is a high speed 1.5 megabit Static

xc6c

Contextual Info: LF2250 12 x 1 0-b it M a t r ix M u l t ip lie r □ 50 M H z D ata a n d C o m p u ta tio n Rate □ N in e M u ltip lier A rray w ith 12-bit D ata a n d 10-bit C oefficient In p u ts □ S e p a rate 16-bit C asc ad e In p u t a n d O u tp u t Ports □ O n -b o a rd C oefficient Storage