XC95XX Search Results

XC95XX

Abstract: BGA95 sb 1240
Contextual Info: 1.400" Top View 0.100" 1.350" 1.350" 1.240" 0.5mm Pitch Relative Orientations BGA Pin A1 Side View 1 QFP Pin 1 0.477" 3 0.6" Assembled 2 0.293" Removable Alignment Pins Description: PACKAGE CONVERTER 208 position PQFP to 352 position BGA. Altera Max 9320 to Xilinx XC95XX.

XC9572

Abstract: XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C
Contextual Info: XC9572 In-System Programmable CPLD R DS065 v4.2 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable

XC95144XL-10TQ144I

Abstract: XC95144XL-10TQG100C XAPP114 XAPP427 XC9500XL XC95144 XC95144XL XC95144XL-5-CS144 XC95144XL-5TQ100 xc95144xl tq144
Contextual Info: XC95144XL High Performance CPLD R DS056 v1.8 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

XC95108

Abstract: XC95108-10PQ160C xc95108-10pqg100i XC95108-20PQG160I TQG100 XC95108-15PC84C PGC84 XC95108-20PQ100I
Contextual Info: – PRODUCT OBSOLETE / UNDER OBSOLESCENCE – XC95108 In-System Programmable CPLD R DS066 v5.0 May 17, 2013 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates

XC9536XL

Abstract: XAPP114 XAPP427 XC9500XL XC9536 Pb-Free Marking Codes XC9536XL VQFP XC9536XL-10VQ64C VQG44 XC9536XL-10VQ44
Contextual Info: XC9536XL High Performance CPLD R DS058 v1.7 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

FEIN FOCUS FXS-100

Abstract: curve tracer equipment XCS17 hypervision visionary 2000 XRF-5500 diode ST2D 77 JMS-6401F JEOL SEM mil-std-883* lead fatigue MS-170
Contextual Info: Quality Assurance and Reliability R February 1, 2000 v3.0 9* Quality Assurance Program All aspects of the Quality Assurance Program at Xilinx have been designed to eliminate the root cause of defects by prevention, rather than to try to remove defects through

XC95288XL pinout

Abstract: XC95288XL XC95288XL-7PQ208I XC95288XL-7TQ144I XC95288XL-10PQ208I XC95288XL-10TQ144I marking G18 XC95288XL-10-PQ208 XC95288XL-6FG256C XAPP114
Contextual Info: XC95288XL High Performance CPLD DS055 v1.7 August 21, 2003 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins)

XC95288XL10TQG144I pinout

Abstract: XC95288XL PQG208 XC95288XL pinout XC95288XL-10TQG144C fgg256 XC95288XL XC95288XL-7CS280C XC95288XL-10FGG256I XC95288XL-7TQ144I pqg208
Contextual Info: XC95288XL High Performance CPLD R DS055 v2.1 April 3, 2007 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins

XC9572

Abstract: xc9572 data sheet XC9572-15PC84C XC9572-7PCG84C XC9572-15PQG100I XC9572-10PQ100C XC9572-7TQG100C XC9572-15PCG44C XC9572-10PQ100I XC9572-10PC44I
Contextual Info: XC9572 In-System Programmable CPLD R DS065 v4.3 April 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable

XC95216-20PQG160I

Abstract: XC95216-15PQ160I 471 E25 XC95216 Family XC95216-10PQ160C XC95216-10PQ160I XC95216-15PQG160C XC95216-15PQG160I XC95216-10PQG160I XC9500
Contextual Info: XC95216 In-System Programmable CPLD R 5 Note: The 352-pin BGA packages are being discontinued for XC95216 devices. You cannot order these packages after May 14, 2008. Xilinx recommends replacing XC95216 in 352-pin BGA packages with XC95288 devices in 352-pin BGA packages in all designs as soon as possible. Recommended replacements are pin compatible, but

Contextual Info: XC9536XV High-performance CPLD R DS053 v2.4 May 27, 2003 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins)

XC95144

Abstract: XC95144-10PQG100I XC95144-10PQG160C xc9514415pqg160i Plastic Quad Flat Pack PQFP XC95144-10TQG100I xc95144-15pqg100i XC95144-7PQG160C XC95144-15PQG160C XC95144-15pqg160i
Contextual Info: XC95144 In-System Programmable CPLD R DS067 v5.6 April 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable

XC95144XL-10TQG100C

Abstract: XC95144XL-10TQ100I XC95144XL-10CSG144C XC95144XL-10TQ144I XC95144XL-5-TQ100 XC95144XL-10TQG144C xc95144xl XC95144XL-10TQG100I XC95144XL-7TQ100C TQFP 100 PACKAGE footprint
Contextual Info: XC95144XL High Performance CPLD R DS056 v2.0 April 3, 2007 Features • • • • • • • • • • • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins)

PC44

Abstract: VQ44 XAPP361 XC9500XV XC9572XV
Contextual Info: XC9572XV High-performance CPLD R DS052 v2.5 August 21, 2003 5 Features • • • • • • • • 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins)

XC95288

Abstract: BG352 HQ208 XC9500 n439
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.1 August 21, 2003 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable

XC9572XL

Abstract: xc9572xl pin configuration XC9572XL-5VQ44C XAPP114 XAPP427 XC9500XL XC9572 XC9572XL-10 XC9572XL-5 XC9572XL-7
Contextual Info: XC9572XL High Performance CPLD R DS057 v1.8 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

PC44

Abstract: XAPP361 XC9500XV XC9536XL XC9536XV B1.66 20E2
Contextual Info: XC9536XV High-performance CPLD R DS053 v2.5 August 21, 2003 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins)

XC95144 PQ100

Abstract: XC95144 XC95144-15TQG100C XC95144-15TQG100I XC95144-10PQ100I PQ100 PQ160 TQ100 XC9500 XC95144-15PQ100
Contextual Info: XC95144 In-System Programmable CPLD R DS067 v5.7 May 28, 2009 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable

471 E25

Abstract: xc95288 XC95288-15HQ208I AD9318 A23 780-4 BG352 HQ208 XC9500 h3144 n439
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.3 April 3, 2006 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable

XC9572

Abstract: XC9572-15PQG100C XC9572-10TQG100I XC9572-15TQG100C XC9572-10PQ100I XC9572 pcg84 XC9572-15PCG84C XC9572-10PQG100C XC9572-15PCG44C XC9572 PC84
Contextual Info: XC9572 In-System Programmable CPLD R DS065 v4.3 April 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable

Contextual Info: Product Obsolete/Under Obsolescence u XC95288XV High-Performance CPLD R DS050 v3.0 June 25, 2007 5 Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC95288XV devices with equivalent XC95288XL

XC9536-10PC44C

Contextual Info: XC9536 In-System Programmable CPLD R DS064 v6.0 June 18, 2003 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins 5V in-system programmable

xilinx MARKING CODE

Contextual Info: XC9536XV High-performance CPLD R DS053 v2.7 January 16, 2006 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint package - 44-pin VQFP (34 user I/O pins) Optimized for high-performance 2.5V systems

Contextual Info: Product Obsolete/Under Obsolescence XC9536XV High-performance CPLD R DS053 v3.0 June 25, 2007 1 Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9536XV devices with equivalent XC9536XL devices