V200E Search Results

XAPP133

Abstract: vhdl code for lvds driver d flip-flop PCI33 PQ240 TQ144 BG352 BG432 CS144 HQ240
Contextual Info: Application Note: Virtex Series R Using the Virtex SelectI/O Resource XAPP133 v2.6 November 5, 2002 Summary The Virtex FPGA series includes a highly configurable, high-performance SelectI/O™ resource to provide support for a wide variety of I/O standards. The SelectI/O resource is a

fundamentals of fdr

Abstract: BG352 BG432 CS144 HQ240 PCI33 PQ240 TQ144 XAPP133 V2000E
Contextual Info: Application Note: Virtex Series R Using the Virtex SelectI/O Resource XAPP133 v2.5 September 7, 2000 Summary The Virtex FPGA series includes a highly configurable, high-performance SelectI/O™ resource to provide support for a wide variety of I/O standards. The SelectI/O resource is a

2S100PQ208

Abstract: 2S200EPQ208-6C 2S50PQ208-5C 2S50PQ208 PCI32 PCI64 2S100EPQ208-6C 2S50PQ208-5 2S100PQ208-5C 2s200pq208-5
Contextual Info: LogiCORE PCI32 Interface v3.0 DS 206 v1.2 July 19, 2002 Introduction Data Sheet, v3.0.100 LogiCORE Facts With the Xilinx LogiCORE PCI Interface, a designer can build a customized, fully PCI 2.3-compliant core with the highest possible sustained performance, 528 Mbytes/sec.

verilog code for stream processor

Abstract: LIN source code LIN ACTUATORS XC3S250E V200E LIN verilog source code verilog code for frame synchronization
Contextual Info: Support of LIN specification 2.0 Programmable data rate between 1 Kbit/s and 20 Kbit/s LIN 8-byte data buffer Controller Core Configurable for support of master or slave functionality 8-bit host controller interface Slave can be implemented with or without clock synchronization

verilog code for lvds driver

Abstract: BG352 BG432 CS144 HQ240 PCI33 PQ240 TQ144 XAPP133 3state buffer vhdl code
Contextual Info: Application Note: Virtex Series R XAPP133 v2.1 January 19, 1999 Using the Virtex SelectI/O Application Note Summary The Virtex FPGA series includes a highly configurable, high-performance I/O resource, called SelectI/O to provide support for a wide variety of I/O standards. The SelectI/O resource is a

enpac 1200

Abstract: Rockwell ENPAC 2500 EK-48626 Rockwell emonitor disadvantage of numeric water level indicator 102A053 map diagram RPM meter EK-48623 enpac 2500 EK-48624
Contextual Info: Enpac Ex Data Collector Your manual for using the Enpac Ex with Emonitor Users Guide Important User Information Solid state equipment has operational characteristics differing from those of electromechanical equipment. Safety Guidelines for the Application, Installation and

interfacing cpld xc9572 with keyboard

Abstract: VERIFY 93K template 34992 XC95288XL evaluation board schematic XCR3032C XcxxX xilinx logicore core dds XC2S15-VQ100 creative labs model 3400 FXS-100
Contextual Info: The Programmable Logic Data Book 2000 R R , XC2064, NeoCAD PRISM, XILINX Block Letters , XC-DS501, NeoROUTE, XC3090, FPGA Architect, XC4005, FPGA Foundry, XC5210, Timing Wizard, NeoCAD, TRACE, NeoCAD EPIC, XACT are registered trademarks of Xilinx, Inc. , all XC-prefix product designations, AllianceCore, Alliance Series, BITA, CLC, Configurable Logic Cell, CoolRunner, Dual Block, EZTag, Fast CLK, FastCONNECT,

intel 8051 Arithmetic and Logic Unit -ALU

Abstract: 4 bit microcontroller using vhdl design an 8 Bit ALU using VHDL software tools ALU VHDL And Verilog codes microcontroller using vhdl 32 BIT ALU design with vhdl 8 bit data bus using vhdl 32 bit alu using vhdl 16 bit data bus using vhdl 80C51
Contextual Info: Compact D80530C Microcontroller March 21, 2000 Product Specification AllianceCORE Facts CAST, Inc. 24 White Birch Drive Pomona, New York 10907 USA Phone: +1 914-354-4945 Fax: +1 914-354-0325 E-Mail: info@cast-inc.com URL: www.cast-inc.com Features • •

K2466

Abstract: H1342 AU61
Contextual Info: 901592 Virtex -E 1.8 V Field Programmable Gate Arrays R DS022 v1.5 July 10, 2000 3* Features Preliminary Product Specification High-performance Built-in Clock Management Circuitry - Eight fully digital Delay-Locked Loops (DLLs) • Fast, High-density 1.8 V FPGA Family

Contextual Info: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies DCT-FI  Low gate count 2D Forward and Inverse Discrete Cosine Transform Core  Low latency (89 cycles)  Single clock cycle per sample operation on both directions

2S1006

Abstract: XIP2018
Contextual Info: AES Encryption Core January 29, 2002 Product Specification AllianceCORE Facts CAST, Inc. 11 Stonewall Court Woodcliff Lake, NJ 07677 USA Phone: 201-391-8300 Fax: 201-391-8694 E-mail: info@cast-inc.com URL: www.cast-inc.com Features • • • • • •

vhdl code for DES algorithm

Abstract: verilog code for implementation of des verilog code for des vhdl code for des decryption
Contextual Info: x_3des.fm Page 1 Saturday, February 3, 2001 1:11 PM X_3 DES Triple DES Cryptoprocessor February 9, 2001 Product Specification AllianceCORE Facts 11 E. Plumeria Drive San Jose, CA 95134 USA Phone: +1 408-894-1900 In US: +1 800-677-7305 Fax: +1 408-570-1230

K363 equivalent

Abstract: n345 AF125 XCV1000E d30122 A281 horizontal driver transistor D155 AY102 j281 pioneer amplifier an214
Contextual Info: Virtex -E 1.8 V Field Programmable Gate Arrays R DS022 v1.7 September 20, 2000 Preliminary Product Specification Features • • • • • • Fast, High-Density 1.8 V FPGA Family - Densities from 58 k to 4 M system gates - 130 MHz internal performance (four LUT levels)

dct verilog code

Contextual Info: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies DCT  Low gate count  Single clock cycle per sample 2-D Forward Discrete Cosine Transform Core operation  Low latency (87 cycles) Design Quality The DCT core implements the 2D Forward Cosine Transform. Most of the image/video

63B29

Abstract: pioneer amplifier an214 H336 transistor tt 2222 AF125 XCV1600E AN214 AN214 amplifier bb244 diode t25 4 F6
Contextual Info: 901592 Virtex -E 1.8 V Field Programmable Gate Arrays R DS022 v1.3 February 29, 2000 3* Features Advance Product Specification • High-performance Built-in Clock Management Circuitry - Eight fully digital Delay-Locked Loops (DLLs) • Fast, High-density 1.8 V FPGA Family

B1348

Abstract: barco 8x8 sram vhdl coding for pipeline IDCT xilinx 1180-1990
Contextual Info: DCT_IDCT 2D February 8, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Documentation Design File Formats Verification Constraints File Instantiation Templates Reference designs & application notes Additional Items

baugh-wooley multiplier verilog

Abstract: 1BG25 LPQ100 9572xv BC356 LPQ240 block diagram baugh-wooley multiplier 4 BIT ALU design with vhdl code using structural XC3000A actel a1240
Contextual Info: LeonardoSpectrum Synthesis and Technology v1999.1 Copyright Copyright 1991-1999 Exemplar Logic, Inc., A Mentor Graphics Company All Rights Reserved Trademarks Exemplar Logic and its Logo are trademarks of Exemplar Logic, Inc. LeonardoSpectrum™, LeonardoInsight™, FlowTabs™, HdlInventor™, SmartScripts™,

ao21

Abstract: XCV300E-6PQ240C
Contextual Info: Virtex -E 1.8 V Field Programmable Gate Arrays R DS022 v1.6 August 1, 2000 Preliminary Product Specification Features • • • - Densities from 58 k to 4 M system gates - 130 MHz internal performance (four LUT levels) - Designed for low-power operation

AN3130

Abstract: B205 AN214 amplifier circuit diagram XCV600E-FG900 XCV1000E XCV1600E X901 d33b29
Contextual Info: 2 Virtex -E 1.8 V Field Programmable Gate Arrays R DS022 v1.1 January 10, 2000 3* Features Advance Product Specification • High-performance Built-in Clock Management Circuitry - Eight fully digital Delay-Locked Loops (DLLs) • Fast, High-density 1.8 V FPGA Family

vhdl code for parity checker

Abstract: SPARTAN 6 Configuration transistor 6c x verilog hdl code for parity generator Spartan-II pin details vhdl code for 9 bit parity generator Virtex 5 for Network Card 2s200pq208-5 2S200EPQ208-6C vhdl code for 4 bit even parity generator
Contextual Info: LogiCORE PCI32 Interface v3.0 DS206 April 14, 2003 Introduction Data Sheet, v3.0.106 LogiCORE Facts With the Xilinx LogiCORE PCI Interface, a designer can build a customized, fully PCI 2.3-compliant core with the highest possible sustained performance, 528 Mbytes/sec.

16 bit single cycle mips vhdl

Abstract: 8051 control unit frequency counter using 8051 verilog code for UART baud rate generator xilinx baud generator verilog code uart vhdl fpga intel 8051 Arithmetic and Logic Unit -ALU R8051 xilinx 8051 80C31
Contextual Info: r8051.fm Page 1 Thursday, November 30, 2000 2:09 PM R8051 Microcontroller December 5, 2000 Product Specification AllianceCORE Facts CAST, Inc. 75 N. Broadway Nyack, NY 10960 Tel: 845-353-6160 Fax: 845-727-7607 E-Mail: info@cast-inc.com URL: www.cast-inc.com

XAPP133

Abstract: CG560 CB228 CS144 HQ240 PCI33 PQ240 TQ144
Contextual Info: Application Note: Virtex Series R Using the Virtex SelectI/O Resource XAPP133 v2.7 June 9, 2005 Summary The Virtex FPGA series includes a highly configurable, high-performance SelectI/O™ resource to provide support for a wide variety of I/O standards. The SelectI/O resource is a

SK100 transistor

Abstract: C125T-A rb342a stc 1740 k0389 l9150 St4540 st l9150 transistor nec 8772 MNT S100
Contextual Info: Cooper Crouse-Hinds Cross Reference Competitor: Adalet Competitor Catalog Number XFC-210 ECGJH110 XFC-212 ECGJH112 XFC-215 ECGJH115 XFC-218 ECGJH118 XFC-221 ECGJH121 XFC-224 ECGJH124 XFC-227 ECGJH127 XFC-230 ECGJH130 XFC-233 ECGJH133 XFC-236 ECGJH136 XFC-24 ECGJH14