J281 Search Results

DG28

Abstract: MJ2812 MJ2812HS
Contextual Info: Ä PLESSEY W Semiconductors > J2812HS 32 WORDS x 8 BIT FIFO MEMORY T h e M J2812H S is a high speed version of the M J2812 32w ord by 8 -bit first-in first-out m em ory. Th e device has com pletely independent read and write controls and three state outputs controlled by an output enable pin O E . Data

J2812

Contextual Info: PLESSEY SE MIC O N D U C T OR S T5 D e | 72ED513 □□Dtt75 fl J ~ 95D 0 6 6 7 5 7 2 2 0 5 1 3 PLESSEY SEMICONDUCTORS J2812, J2812M 32 WORDS 8 BIT FIFO MEMORY J2813, J2813M 32 WORDS x 9 BIT FIFO MEMORY X The M J2812 and M J2813 are 32-word by 8-bit and 9-bit

Contextual Info: QUINT LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR DESCRIPTION FEATURES • ■ ■ ■ ■ ■ SY100E417 3.3V and 5V power supplies required Also, supports LVPECL-to-PECL translation 500ps propagation delays Fully differential design Differential line receiver capability

Contextual Info: * SYNERGY S E M IC O N D U C T O R 125 MHz WRITE P R O G R A MM A B L E TIMING EDGE VERNIER DESCRIPTION FEATURES • True 125MHz retrigger rate ■ Pin-com patible with Bt605 ■ 15ps delay resolution ■ Less than ± 1 LSB tim ing accuracy ■ Differential TRIGGER and delay W RITE inputs

Contextual Info: * DUAL SUPPLY SYNERGY o c ta l e c l-to -ttl S E M IC O N D U C T O R Clockworks s y io o h a b « SY100HA643 DESCRIPTION FEATURES E C L /T T L v e rs io n o f p o p u la r E C L in P S ™ E 1 11 4 0 0 p s w ith in d e v ic e sk ew 8 0 0 p s p a rt-to -p a rt s k e w

Contextual Info: .M i P ln r k W n r k c ^ 3.3V SINGLE SUPPLY 1:9 PECL-TO-TTL SYNERGY PRELIMINARY SY10H641L SY100H641L SEM ICONDUCTOR FEATURES DESCRIPTION • 3 .3 V p o w e r s u p p ly ■ P E C L -to -T T L v e rs io n o f p o p u la r E C L in P S E111 ■ G u a ra n te e d lo w s k e w s p e c ific a tio n

Contextual Info: * PROGRAMMABLE DELAY CHIP SYNERGY SEM IC O N D U C TO R FEATURES • ■ C lo c k w o r k s ' SY10E195 S Y 10Q E 195 DESCRIPTION Up to 2ns d e la y range 2 0 p s /d ig ita l s te p re s o lu tio n ■ >1 GHz b a n d w id th ■ O n -c h ip c a sca d e c irc u itry

Contextual Info: * S IN G L E S U P P L Y O C T A L SYNERGY Cloc* ° r* ™ P E C L /T T L -tO -T T L SY100H646 S E M IC O N D U C T O R FEATURES • PECL/TTL-to-TTL version of popular ECLinPS E111 ■ Meets specifications required to drive highperformance x86 processors

LD 757 ps

Contextual Info: * LOW POW ER HEX TTL-to-ECL TRANSLATO R SYNERGY SY100S324 S E M IC O N D U C T O R DESCRIPTION FEATURES Max. propagation delay of 1.4ns The SY100S324 is a hex translator designed to convert T T L logic levels to 100K ECL levels. The inputs are TTL com patible with diffe re n tia l o utputs that can e ith e r be

Contextual Info: * 9-BIT LATCHED ECL-TO -TTL SYNERGY SY10H603 SY100H603 S E M IC O N D U C T O R FEATURES DESCRIPTION 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise Dual supply

100E196

Contextual Info: * C lo c k w o rk s SY10E196 SY100E196 P R O G R A M M A B L E DELAY CHIP WITH A N A L O G INPUT SYNERGY S E M IC O N D U C T O R DESCRIPTION FEATURES • Up to 2ns delay range ■ Extended 100E V ee range of -4.2V to -5.5V ■ ~20ps digital step resolution

Contextual Info: * DUAL PHASE LOCKED LOOP SYNERGY S E M IC O N D U C T O R FEATURES DESCRIPTION 3.3V and 5V power supply options 1.12GHz maximum VCO frequency 30 to 560MHz reference input operating frequency Frequency doubler mode Low jitter design PECL differential outputs

E160

Abstract: SY100E160 SY10E160 SY10E160JC
Contextual Info: 12-BIT PARITY GENERATOR/CHECKER DESCRIPTION FEATURES • Provides odd-HIGH parity of 12 inputs ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E160 are high-speed, 12-bit parity generator/checkers with differential outputs, for use in new, high-performance ECL systems. The output Q takes

F100K

Abstract: SY100S304 SY100S304FC SY100S304JC SY100S304JCTR
Contextual Info: QUINT AND/NAND GATE FEATURES SY100S304 DESCRIPTION • Max. propagation delay of 1050ps ■ IEE min. of –60mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity ■ Internal 75KΩ input pull-down resistors

F100K

Abstract: SY100S301 SY100S301FC SY100S301JC SY100S301JCTR F100K ECL book
Contextual Info: TRIPLE 5-INPUT OR/NOR GATE SY100S301 DESCRIPTION FEATURES • Max. propagation delay of 750ps ■ IEE min. of –25mA ■ Industry standard 100K ECL levels ■ Extended supply voltage option: VEE = –4.2V to –5.5V The SY100S301 is an ultra-fast triple 5-input OR/NOR

F100K

Abstract: SY100S336 SY100S336FC SY100S336JC SY100S336JCTR
Contextual Info: 4-STAGE COUNTER/ SHIFT REGISTER FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The SY100S336 functions either as a modulo-16 up/ down counter or as a 4-bit bidirectional shift register and is designed for use in high-performance ECL systems. Three

F100K

Abstract: SY100S321 SY100S321FC SY100S321JC SY100S321JCTR
Contextual Info: LOW-POWER 9-BIT INVERTER FEATURES SY100S321 DESCRIPTION • Max. propagation delay of 700ps ■ IEE min. of –55mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity ■ 70% faster than Fairchild 300K at lower power

F100K

Abstract: SY100S302 SY100S302FC SY100S302JC SY100S302JCTR
Contextual Info: QUINT 2-INPUT OR/NOR GATE FEATURES The SY100S302 offers five 2-input OR/NOR gates designed for use in high-performance ECL systems. The five gates are controlled by a common Enable signal. All inputs have 75KΩ pull-down resistors and all outputs are buffered.

E160

Abstract: E193 MC10193 SY100E193 SY10E193
Contextual Info: Micrel, Inc. SY10E193 SY100E193 SY10E193 ERROR DETECTION/ CORRECTION CIRCUIT FEATURES SY100E193 DESCRIPTION • Hamming code generation ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E193 are error detection and correction EDAC circuits designed for use in new, high- performance

F100K

Abstract: SY100S350 SY100S350FC SY100S350FCTR SY100S350JC
Contextual Info: Micrel, Inc. SY100S350 FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S350 HEX D-LATCH DESCRIPTION The SY100S350 offers six high-speed D-Latches with both true and complement outputs, and is performance compatible for use with high-performance ECL systems.

SY100S811

Abstract: SY100S811JC SY100S811ZC Q7920
Contextual Info: SINGLE SUPPLY 1:9 PECL/TTL-TO-PECL Micrel, Inc. Precision Edge Precision SY100S811 Edge® SY100S811 FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PECL version of popular ECLinPS E111 Low skew Guaranteed skew spec VBB output TTL enable input Selectable TTL or PECL clock input

SY89429V

Abstract: SY89429VJC SY89429VJCTR SY89429VJZ SY89429VZC SY89429VZCTR
Contextual Info: Micrel, Inc. 5V/3.3V PROGRAMMABLE FREQUENCY SYNTHESIZER 25MHz to 400MHz Precision Edge SY89429V ® Precision Edge SY89429V FEATURES • ■ ■ ■ ■ ■ ■ ■ 3.3V and 5V power supply options 25MHz to 400MHz differential PECL outputs 50ps peak-to-peak output jitter

F100K

Abstract: SY100S325 SY100S325FC SY100S325FCTR SY100S325JC
Contextual Info: LOW-POWER HEX ECL-to-TTL TRANSLATOR Micrel, Inc. DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Max. propagation delay of 3.7ns IEE min. of –37mA TTL outputs Extended supply voltage option: VEE = –4.2V to –5.5V 25% faster than National's 325

Contextual Info: * TRIPLE 5-INPUT OR/NOR GATE SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 750ps Iee SY100S301 min. o f-25 m A Industry standard 100K ECL levels T h e S Y 1 0 0 S 3 0 1 is an u ltra -fa s t triple 5 -in p u t O R /N O R g a te d e s ig n e d for use in h ig h -p e rfo rm a n c e E C L system s.