DS206 Search Results

DS2064

Contextual Info: DALLAS SEMICONDUCTOR 4401 South Beltwood Parkway Dallas, Texas 75244–3292 214 450–0400 Date: July 2, 1996 Subject: PRODUCT CHANGE NOTICE – E63001 Description: Product Obsolescence: DS2064 Low–Voltage Option Description of Change: Effective September 30, 1996, all DS2064 devices will become 5–volt–only products. All low–voltage specifications for both AC and DC parameters will be removed from the DS2064 Data Sheet and

K19 FET

Abstract: plc fire protection DS1265W DS2065W DS2065W-100
Contextual Info: Rev 0; 1/05 DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM Features The DS2065W is a 8Mb reflowable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in

ram 2064

Abstract: Static RAM 2064
Contextual Info: DS2064 DALLAS SEMICONDUCTOR FEATURES DS2064 8K x 8 Static RAM PIN ASSIGNMENT • Low power CM OS design • Standby current 50 nA max at tA = 25°C 100 nA max at tA = 25°C 1 max at tA = 60°C Vc c = 3.0V V qq = 5.5V Vc c = 5.5V • Full operation for V c c = 4.5V to 5.5V

CS8952

Abstract: CS8952-IQ
Contextual Info: 08/14/00 Errata: CS8952-IQ Performance Update Reference CS8952 Data Sheet revision DS206PP2 dated Jul ’98 • Add part number to Ordering Information on page 1 of the datasheet. - CS8952-IQ -40° C to +85° C 100-pin TQFP • On page 4, add the following row to the RECOMMENDED OPERATING

XC6SLX9-TQG144-2C

Abstract: XC6SLX45-CSG324 XC6SLX16-CSG225 XC6SLX16-FTG256 XC6SLX16-CSG324 XC6SLX4-TQG144-2C XC6SLX45-CSG484 XC6SLX9-CSG225 XC3S1400A-FG676-4C/I XC6SLX45-FGG484
Contextual Info: 32-Bit Initiator/Target v3 & v4 for PCI DS206 December 2, 2009 Product Specification v3.167 & v4.11 Features • Fully compliant 32-bit, 66/33 MHz Initiator/Target core for PCI • Customizable, programmable, single-chip solution • Pre-defined implementation for predictable timing

XC7K325TFFG900

Abstract: XC6SLX45-CSG324 XC3SD3400AFG676 XC7K325T-ffg900 spartan ucf file 6 XC6SLX16-FTG256 XC6SLX25-CSG324-2C XC6SLX16-CSG324 XC6SLX45-FGG484 XC7K355T-FFG901
Contextual Info: LogiCORE IP 32-Bit Initiator/Target v3 & v4 for PCI DS206 October 19, 2011 Product Specification v3.167 & v4.15 Features LogiCORE IP Facts Table • Fully compatible 32-bit, 66/33 MHz Initiator/Target core for PCI • Customizable, programmable, single-chip solution

DS2064

Abstract: DS2064S
Contextual Info: DS 2064 DALLAS DS2064 8K x 8 Static RAM SEMICONDUCTOR PIN ASSIGNMENT FEATURES • Low pow er C M OS design • S tandby current 50 nA max at tA = 25°C 100 nA max at tA = 25°C 1 nA max at tA = 60°C V Cc = 3.0V V Cc = 5.5V V q c = 5.5V □ V cc 27 □ WE

Contextual Info: DS2064, DS2064S DALLAS SEMICONDUCTOR DS2064, DS2064S 8K x 8 FEATURES 3V Operation Static RAM PIN ASSIGNMENT • Low power CMOS design • Standby current NC C 1 28 A12 C 2 27 A7 C 3 26 A 6C 4 25 A5 L 5 24 50 nA max at tA = 25°C Vcc = 3.0V 100 nA max at tA = 25°C Vcc = 5.5V

XC2S150pq208

Abstract: xc2s50-pq208 XCV1000EFG680-6C XC2S150PQ208-5C XC2S200ePQ208 XC2S300EPQ208-6C xcv1000efg680 XCV300BG432 2S50E-PQ208-6C XC3S1000-FG456-4C
Contextual Info: LogiCORE PCI32 Interface v3.0 DS206 October 28, 2003 Introduction Data Sheet, v3.0.116 LogiCORE Facts With the Xilinx LogiCORE PCI Interface, a designer can build a customized, fully PCI 2.3-compliant core with the highest possible sustained performance, 528 Mbytes/sec.

DIN 65536

Abstract: FA 600 DS2064 DS2064S
Contextual Info: DS2064 DS2064 8K x 8 Static RAM FEATURES PIN ASSIGNMENT • Low power CMOS design • Standby current NC 1 28 VCC A12 2 27 WE A7 3 26 CE2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 • Data Retention Voltage = 5.5V to 2.0V A3 7 22 OE A2 8 21 A10 • Access time equals 200 ns at 5.0V

DS2068

Abstract: DS2068S 8K X 8 Static RAM 100N 100NS H000402 for 64K RAM RAM64K 90-2068S DALLAS SOIC PRODUCT CHANGE
Contextual Info: DALLAS SEMICONDUCTOR 4401 South Beltwood Parkway Dallas, Texas 75244-3292 972 371-4000 Date: July 10, 2000 Product Change Notice – H000402 Subject: Product Obsolescence – DS2068 8K x 8 Static RAM Description of Change: Effective July 10, 2000 Dallas Semiconductor will no longer produce the DS2068 8K x 8 Static

DS2064

Abstract: DS2064S H50801
Contextual Info: DALLAS SEMICONDUCTOR 4401 South Beltwood Parkway Dallas, Texas 75244–3292 214 450–0400 Date: September 19, 1995 Subject: PRODUCT CHANGE NOTICE – H50801 Description: DS2064 and DS2064S Change Description of Change: This change affects DS2064 and DS2064S devices only. Operating current (Icco) will change to 70mA

Contextual Info: DALLAS SEMICONDUCTOR DS2064 8K x 8 Static RAM FEATURES PIN ASSIGNMENT • Low power CM OS design • Standby current 50 nA m ax at 100 nA max at 1 nA m ax at tA = 25°C tA = 25°C tA = 60°C V Cc = 3.0V V Cc = 5.5V V c c = 5.5V Vcc □ WE 3 26 □ CE2 25 □

DS206

Contextual Info: DALLAS SEMICONDUCTOR DS2064 8K x 8 3V Operation Static RAM PIN ASSIG NM ENT FEATURES Vcc 24 = 6 23 □ A11 7 22 □ • Data Retention Voltage OE A2 C 8 21 □ A10 A1 C 9 20 □ ceT 10 19 □ DQ7 27 C E 3 26 4 25 A5 C 5 A4 C A3 C A7 A6 5.5V to 2.0V • Access time equals 150 ns at 5.0V and 300 ns at 3.0V

CS8952

Abstract: CS8952T 0x19
Contextual Info: Errata: CS8952 - Silicon revision: F Reference CS8952 Data Sheet revision DS206PP3 dated October 2001. Link Status Change Interrupt Description The datasheets for the CS8952 and CS8952T state that an interrupt can be generated on a link status change. This is true for 100 Mbps mode.

Static RAM 2064

Abstract: 2064 eprom
Contextual Info: D S 2064 DALLAS SEMICONDUCTOR DS2064 8K x 8 Static RAM FEATURES PIN ASSIGNMENT • Low power CM OS design • Standby current 50 nA m ax at 100 nA max at 1 nA m ax at tA = 25°C tA = 25°C tA = 60°C V Cc = 3.0V V Cc = 5.5V V c c = 5.5V Vcc □ WE 3 26 □

Contextual Info: DALLAS SEMICONDUCTOR DS2064 8K x 8 3V Operation Static RAM PIN ASSIGNMENT FEATURES • Low power CMOS design • Standby current NC C 1 28 3 Vcc A12 C 2 27 3 WË A7 C 3 26 3 CE2 A6 C 4 25 D A8 3 3 3 3 3 3 3 3 3 3 50 nA max at tA = 25°C Vcc = 3.0V 100 nA max at tA = 25°C Vcc = 5.5V

DALLAS SEMICONDUCTOR Ds1235

Abstract: megatest tester DS1235 ds1630 megatest tester datasheet DS2237 DS1217 dallas ds1230 DS1220 ON SEMICONDUCTOR TRACEABILITY
Contextual Info: DALLAS SEMICONDUCTOR 4401 South Beltwood Parkway Dallas, Texas 75244-3292 972 371-4000 Date: 05/24/97 Subject: PRODUCT CHANGE NOTICE - E71301 Description: Tester Change for DS2016, DS2064, DS2068, and DS2257

DS2064

Abstract: DS2064S
Contextual Info: DS2064 DS2064 8K x 8 Static RAM FEATURES PIN ASSIGNMENT • Low power CMOS design • Standby current NC 1 28 VCC A12 2 27 WE A7 3 26 CE2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 • Data Retention Voltage = 5.5V to 2.0V A3 7 22 OE A2 8 21 A10 • Access time equals 200 ns at 5.0V

2064 ram

Contextual Info: DS2064 DALLAS s e m ic o n d u c to r FEATURES DS2064 8K x 8 Static RAM PIN ASSIGNMENT • Low power CM OS design • Standby current 50 nA max at tA = 25°C 100 nA max at tA = 25°C 1 max at tA = 60°C Vc c = 3.0V V qq = 5.5V Vc c = 5.5V • Full operation for V c c = 4.5V to 5.5V

Contextual Info: DS2064 DALLAS SEMICONDUCTOR DS2064 8K x 8 Static RAM FEATURES PIN ASSIGNMENT • Low power CMOS design 28 □ V cc A12 C 2 27 □ WE A7 C 3 28 CE2 A6 L 4 25 A5 L_ 5 24 A4 C 6 23 ASC 7 22 J 3 J J J A2 C S 21 n A10 A1 C 9 20 AC u 10 19 DQ0 L 11 OQ1 C 12 OQ2 C

Contextual Info: Rev 1; 5/06 DS2065W 3.3V Single-Piece 8Mb Nonvolatile SRAM The DS2065W is a 8Mb reflowable nonvolatile NV SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in

Contextual Info: DALLAS DS2064 8K x 8 Static RAM s e m ic o n d u c t o r FEATURES PIN ASSIGNMENT • Standby current 50 nA max at tA = 25°C V cc = 3.0V 100 nA max at tA = 25°C Vc c = 5.5V 1 |iA max at t* = 60°C V cc = 5.5V • Full operation for V cc = 4-5V to 5.5V • Data Retention Voltage = 5.5V to 2.0V

XC2S200PQ208

Abstract: XC2S100PQ208-5C XC2S50PQ208-5C xc2s50-pq208 XCV300BG432 XC2S200pq208 pin configuration XC2S150PQ208 XCV1000EFG680-6C XC2S100PQ208 PCI32
Contextual Info: LogiCORE PCI32 Interface v3.0 DS206 July 15, 2004 Product Specification v3.0.129 Features LogiCORE Facts • Fully PCI 2.3-compliant core, 32-bit, 66/33 MHz interface PCI32 Resource Utilization 1 • Customizable, programmable, single-chip solution • Predefined implementation for predictable timing