TTL GATE Search Results

HLT28

Abstract: HT28 KLT28 KT28 MC100ELT28 MC10ELT28 MC10ELT28D
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading

HLT28

Abstract: KLT28 MC100 MC100ELT28 MC10ELT28 transistor k 4110
Contextual Info: MC10ELT28, MC100ELT28 5 V TTL to Differential PECL and Differential PECL to TTL Translator Description • • • • • • • • • • 3.5 ns Typical PECL to TTL Propagation Delay 1.2 ns Typical TTL to PECL Propagation Delay PNP TTL Inputs for Minimal Loading

TTLOS

Abstract: ttl_pw TTLOS-50 TTLOS-10 TTLOS-15 TTLOS-20 TTLOS-25 TTLOS-30 TTLOS-33 TTLOS-35
Contextual Info: TTL Gated Oscillators TTL Pulse Width Generator Modules TTL Pulse Width Discriminators These gated oscillators permit synchronization of the output square wave with the high-tolow transition of the enable input. When the enable is high, the output is held high. The

Contextual Info: TTL Gated Oscillators TTL Pulse Width Generator Modules TTL Pulse Width Discriminators These gated oscillators permit synchroniza­ tion of the output square wave with the highto-low transition of the enable input. When the enable is high, the output is held high.

740L6000

Abstract: transistor c2026 c2026 c2026 transistor data 740L6010 transistor equivalent c2026 740L6011 C2026 TRANSISTOR 740L6001 c2037
Contextual Info: HIGH-SPEED LOGIC-TO’LOGIC OPTOCOUPLERS OPTOELECTRONICS TTL BUFFER TTL INVERTER CMOS BUFFER CMOS INVERTER LSTTLto ORDER INFORMATION LOGIC COMPATIBILITY PART NUMBER INPUT OUTPUT TTL 740L6000 LSTTL TTL 740L6001 LSTTL CMOS 740L6010 LSTTL CMOS 740L6011 LSTTL

Contextual Info: TTL TRI-STATE HIGH FREQUENCY CLOCK OSCILLATOR F1100HT The F1100HT Clock Oscillator is designed to drive high frequency TTL applications up to 10 TTL gates . This part has a tri-state enable/disable function on pin 1 to facilitate testing with automatic test equipment (ATE).

100PPM

Abstract: 25PPM F1100HT F1144HT F1145HT
Contextual Info: TTL TRI-STATE HIGH FREQUENCY CLOCK OSCILLATOR F1100HT The F1100HT Clock Oscillator is designed to drive high frequency TTL applications up to 10 TTL gates . This part has a tri-state enable/disable function on pin 1 to facilitate testing with automatic test equipment (ATE).

Contextual Info: TTL TRI-STATE HIGH FREQUENCY CLOCK OSCILLATOR F1100HT The F1100HT Clock Oscillator is designed to drive high frequency TTL applications up to 10 TTL gates . This part has a tri-state enable/disable function on pin 1 to facilitate testing with automatic test equipment (ATE).

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

25PPM

Abstract: F1100HT F1144HT F1145HT 100HT
Contextual Info: TTL TRI-STATE HIGH FREQUENCY CLOCK OSCILLATOR F1100HT The FI 100HT Clock Oscillator is designed to drive high frequency TTL applications up to 10 TTL gates . This part has a tri-state enable/disable function on pin 1 to facilitate testing with automatic test equipment (ATE).

9434

Abstract: CY101E383 EME-6300H
Contextual Info: Reliability Report QTP# 94346/95255, Version 1.0 June, 1996 BiCMOS ECL-TTL/TTL-ECL TRANSLATOR MARKETING PART NUMBERS DESCRIPTION CY101E383 ECL/TTL/ECL Translator and High Speed Bus Driver CY10E383 ECL/TTL/ECL Translator and High Speed Bus Driver CYPRESS SEMICONDUCTOR

DP8481

Contextual Info: DP8481 DP8481 TTL to 10k ECL Level Translator with Latch Literature Number: SNOSBN9A DP8481 TTL to 10k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

Contextual Info: DP8483 DP8483 TTL to 100k ECL Level Translator with Latch Literature Number: SNOSBO1A DP8483 TTL to 100k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

signal path designer

Contextual Info: PRELIMINARY D E V IC E S P E C IF IC A T IO N 320000 SERIES ECL/TTL "TURBO" LOGIC ARRAYS 020000 FEATURES PERFORMANCE SUMMARY PARAMETER Typical gate delay* Maximum toggle frequency Maximum TTL input frequency Maximum TTL output frequency Maximum ECL input frequency

NEC C51A

Abstract: nec inverter schematic F074 marking B007 marking B003 JH-04 UPB6101C
Contextual Info: N É C ELECTRONICS INC 7H c D e | LiMH752S DD0Û110 1 NEC NEC Electronics Inc. T-.42-11-05 //PB 6100 TTL-2 SERIES BIPOLAR TTL GATE ARRAYS March 1985 Revision 1 Description The //PB6100 series features three high-speed, lowpower, TTL-compatible gate arrays using advanced

Contextual Info: FAST TTL Gated Square Wave Generator Module The FAST TTL Gated Square Wave Generator Modules manufactured by Engineered Components Company are designed to provide a square wave output at a given frequency. These generators are both keyable and synchronizable, producing a continuous output train as long as a TTL

Contextual Info: FAST TTL Gated Square Wave Generator Module The FAST TTL Gated Square Wave Generator Modules manufactured by Engineered Components Company are designed to provide a square wave output at a given frequency. These generators are both keyable and synchronizable, producing a continuous output train as long as a TTL

Contextual Info: DS75365 DS75365 Quad TTL-to-MOS Driver Literature Number: SNOSBR5A DS75365 Quad TTL-to-MOS Driver Y The DS75365 is a quad monolithic integrated TTL-to-MOS driver and interface circuit that accepts standard TTL input signals and provides high-current and high-voltage output

IC TTL 74LS00

Abstract: TTL LS 7400 IC TTL 74 ls 04 7400 fan-out cmos 7400 fan-out TTL 7400 catalog TTL 74ls00 TTL 7400 rise and fall time of ic 74ls00 74LS00 gate
Contextual Info: Design Considerations, Testing and Applications Assistance Form FAST AND LS TTL FAST AND LS TTL DATA 3-1 3 DESIGN CONSIDERATIONS SELECTING TTL LOGIC. TTL Families may be mixed in a system for optimum performance. For instance, in new designs, ALS would commonly be used in non-critical speed paths to minimize power consumption while FAST TTL would be used in high

Contextual Info: F1100HT / TTL TRI-STATE HIGH FREQUENCY CLOCK OSCILLATOR The new FOX F I 100HT Clock O scillator is designed to drive high frequency TTL applications up to 10-TTL gates . This part has a Tri-State Enable/Disable function on pin 1 to facilitate testing with autom atic test equipm ent

Square Wave Generator

Contextual Info: Space Saver FAST TTL Gated Square Wave Generator The Space Saver FAST TTL Gated Square Wave Generators manufactured by Engineered Components Company are designed to provide a square wave output at a given frequency. These generators are both keyable and synchronizable, producing a continuous output train as long as a TTL

Square Wave Generator

Contextual Info: FAST TTL Gated Square Wave Generator The FAST TTL Gated Square Wave Generators manufactured by Engineered Components Company are designed to provide a square wave output at a given frequency. These generators are both keyable and synchronizable, producing a continuous output train as long as a TTL “low” is applied

uPB6101C

Abstract: NEC C51A N021C F010 nec inverter schematic nec lot code format T-42-11-05
Contextual Info: N É C ELECTRONICS INC 7H D e | LiMH752S DD0Û110 1 NEC N E C Electronics Inc. c T-.42-11-05 //PB 6100 TTL-2 SERIES BIPOLAR TTL GATE ARRAYS March 1985 Revision 1 Description The //PB6100 series features three high-speed, lowpower, TTL-compatible gate arrays using advanced

KLT28

Abstract: HLT28 HT28 KT28 MC100ELT28 MC10ELT28 transistor k 4110
Contextual Info: MC10ELT28, MC100ELT28 5V TTL to Differential PECL and Differential PECL to TTL Translator The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL Positive ECL levels are used, only +5 V and ground are