DP8483 Search Results

Contextual Info: DP8483 S3 National ÆÆ Semiconductor DP8483 TTL to 100k ECL Level Translator with Latch General Description Features This circuit translatas TTL input levels to ECL output levels and provides a fail-through latch. The outputs are gated with CS providing for wire ORing of outputs. The strobe and chip

Contextual Info: DP8483 DP8483 TTL to 100k ECL Level Translator with Latch Literature Number: SNOSBO1A DP8483 TTL to 100k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

MA1040

Abstract: C1995 DP8483 DP8483F DP8483J DP8483M DP8483N J16A M16B N16A
Contextual Info: DP8483 TTL to 100k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with CS providing for wire ORing of outputs The strobe and chip

Contextual Info: DP8483 TTL to 100k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with CS providing for wire ORing of outputs The strobe and chip

Level Translators

Abstract: DS78L12 MM74C901 10K ECL DS88L12 DS3630 CMOS Hex Inverting Buffer MM74C906 cmos tristate inverter DP8481
Contextual Info: Level Translators/Buffers National Æ Æ Semiconductor Level Translators/Buffers Device Number Logic Function 0°Cto +70°C —55°C to + 125°C Output Characteristics Output Input Page Number DP8480A Inverting TRI-STATE Fall Through Latch TTL 10k ECL 7-5