TSU7 SAT Search Results

mitsumi tsu7

Abstract: TSU7 FM DEMODULATOR
Contextual Info: MITSUMI Super Compact, for VCR Use, 2nd RF Units for DBS Receiver TSU7 Series DBS 2nd RF Units, CATV Converters OUTLINE TSU7 series RF units are designed as lightweight and subminiaturized units for receiving satellite broadcast by assembling a conventional second

mitsumi tsu7

Abstract: FM DEMODULATOR
Contextual Info: MITSUMI Super Compact, for VCR Use, 2nd RF Units For DBS Receiver TSU7 Series DBS 2nd RF Units, CATV Converters OUTLINE TSU7 series RF units are designed as lightweight and subminiaturized units for receiving satellite broadcast by assembling a conventional second

T4T15

Contextual Info: RISCoreTM32300 Family Integrated Processor HDWXU WXUHV 79RC32334 ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – MIPS32 Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

Contextual Info: RISCoreTM32300 Family Integrated Processor HDWXU WXUHV 79RC32334 ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

Contextual Info: RISCoreTM32300 Family Integrated Processor HDWXU WXUHV 79RC32334 ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

79RC32334

Abstract: FCT245 MIPS32 RC32300 RC32364 RC5000 SDRAM controller 32bit 16MB
Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334 Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 256MB total SDRAM memory supported

Mem 5116

Abstract: IDT79RC32134 RC32364
Contextual Info: RISCore32300TM Family System Controller Chip HDWXU WXUHV IDT79RC32134 – – 8/16/ or 32-bit interface per bank Supports Flash ROM, SRAM, dual-port memory, and peripheral devices – Intel or Motorola style IO supports external wait-state generation ◆ 4 DMA Channels

IDT79RC32134

Abstract: RC3041 RC32364 RC4640 RC4650 RC64474 RC64475
Contextual Info: IDT79RC32134 RISCore32300TM Family System Controller Chip
   – 8/16/ or 32-bit interface per bank – Supports Flash ROM, SRAM, dual-port memory, and peripheral devices – Intel or Motorola style IO supports external wait-state generation

79RC32334

Abstract: FCT245 MIPS32 RC32300 RC32364 RC5000
Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334 Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 256MB total SDRAM memory supported

Contextual Info: RISCoreTM32300 Family Integrated Processor HDWXU WXUHV 79RC32334 ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

Contextual Info: RISCoreTM32300 Family Integrated Processor HDWXU WXUHV 79RC32334 ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334 Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 256MB total SDRAM memory supported

RC32300

Abstract: 79RC32334 FCT245 MIPS32 RC32364 RC5000 16550 initialization
Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334 Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 256MB total SDRAM memory supported

Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334—Rev. Y Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

ejtag

Abstract: 79RC32334 FCT245 MIPS32 RC32300 RC32364 RC5000 IDT79RC32V334
Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334 Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 256MB total SDRAM memory supported

RC32134

Contextual Info: IDT79RC32134 RISCore32300TM Family System Controller Chip HDWXU WXUHV – – 8/16/ or 32-bit interface per bank Supports Flash ROM, SRAM, dual-port memory, and peripheral devices – Intel or Motorola style IO supports external wait-state generation ◆ 4 DMA Channels

T4T15

Contextual Info: RISCoreTM32300 Family Integrated Processor HDWXU WXUHV 79RC32334 ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions

79RC32334

Abstract: FCT245 MIPS32 RC32300 RC32364 RC5000
Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334 Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 256MB total SDRAM memory supported

79RC32334

Abstract: FCT245 MIPS32 RC32300 RC32364 RC5000
Contextual Info: 79RC32334—Rev. Y IDTTM InterpriseTM Integrated Communications Processor Features Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

RC32300

Abstract: EJTAG RC32364 RC5000 79RC32334 FCT245 MIPS32
Contextual Info: 79RC32334—Rev. Y IDTTM InterpriseTM Integrated Communications Processor Features Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

EJTAG

Abstract: 79RC32334 FCT245 MIPS32 RC32300 RC32364 RC5000 n10n
Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334—Rev. Y Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

Contextual Info: 79RC32334—Rev. Y IDTTM InterpriseTM Integrated Communications Processor Features Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported

Contextual Info: IDT T M InterpriseT M Integrated Communications Processor Features 79RC32334—Rev. Y Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-in terle aved – Up to 512M B total SDRAM memory supported

Contextual Info: RISCoreTM32300 Family Integrated Processor Features 79RC32334—Rev. Y Preliminary Information* Programmable I/O PIO – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported