TSOP 338 IR Search Results

LH5168D-10L

Abstract: tsop 338 IR LH5168 LH5168H
Contextual Info: SHARP CORP h lE LH5168 FEATURES • 8,192 • Access times: 80/100 ns MAX. • Low-power consumption: Operating: 303 mW (MAX.) LH5168/D/N @ 80 ns 248 mW (MAX.) LH5168/D/N/T/TR @ 100 ns 275 mW (MAX.) LH5168H/HD/HN @ 100 ns Standby: 5.5 jiW (MAX.) LH5168/D/N/T/TR

A Listing and Cross Reference of Available Technical Literature from ON Semiconductor

Abstract: MMDF3N06VL MMSF4205 MMSF4P01HDR1 MTP75N06HD MTB3N100E mtd1p50e transistor book transistor SOT23 TO4 36 IGBT Manual
Contextual Info: SG385/D Rev. 3, Jul-2000 Low Voltage Surface Mount TMOS Power MOSFET Selector Guide ON Semiconductor Featuring MiniMOS™ SO-8 , EZFET™, Micro8™, SOT-223, TSOP-6, SOT-23, SC-70/SOT-323, DPAK and D2PAK Low Voltage Surface Mount MOSFETs t TMOS Power MOSFETs

Contextual Info: PRELIMINARY KM6161002A CMOS SRAM 64 K x 16 Bit High-Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time 12,15,17,20 ns Max. • Low Power Dissipation Standby (TTL) : 30 mA(Max.) (CMOS): 10 mA(Max.) Operating KM6161002A-12 : 220 mA(Max.)

M5M27C102J15

Contextual Info: MITSUBIHI LSIs M 5 M 2 7 C 1 0 2 P ,F P ,J ,V P ,R V -1 5 1048576-BIT 65536-WORD BY 16-BIT CMOS ONE TIME PROGRAMMABLE ROM DESCRIPTION The M itsubishi M 5M 27C 102P , FP, J , VP, R V - 15 are h ig h ­ speed 1 0 4 8 5 7 6 - b it one time programmable read only

Contextual Info: Preliminary information •■ I l A S4C4M 4E0 AS4C4M4E1 A 4 M x 4 C M O S DRAM EDO family Features • Organization: 4,194,304 words x 4 bits • High speed • TTL-compatible, three-state I/O • JEDEC standard package - 5 0 / 6 0 ns access tim e - 2 5 / 3 0 ns colum n address access time

1010-SG

Abstract: ic p26 pin 20 transformer 20 pin MSM7541 MSM7541GS MSM7541GS-VK MSM7541RS MSM7542 MSM7542GS MSM7542RS
Contextual Info: O K I Semiconductor MSM7541 / MSM7542 3V Sin g le-R ail PCM C O D E C s D ESCRIPTIO N The MSM7541 and MSM7542 are single-rail, low-voltage, single-channel PCM CODECs which perform voice digitization using presampling and reconstruction filters for transmit and receive operations in

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT ju P D 4 2 S 1 6 4 0 5 L , 4 2 1 6 4 0 5 L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, HYPER PAGE MODE DESCRIPTION The //PD42S16405L, 4216405L are 4 194 304 words by 4 bits dynamic CMOS RAMs with optional hyper page

MSM51V17800

Contextual Info: O K I Semiconductor MSM51 V17800 _ 2,097,152-Word x 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM51V17800 is a 2,097,152-word x 8-bit dynamic RAM fabricated in OKI's CMOS silicon gate technology. The MSM51V17800 achieves high integration, high-speed operation, and low-power

Hyundai central locking

Abstract: bit 3501 Architecture HY29DL162 HY29DL163
Contextual Info: HY29DL162/HY29DL163 16 Megabit 2M x 8/1M x16 Low Voltage, Dual Bank, Simultaneous Read/Write, Flash Memory KEY FEATURES n Single Power Supply Operation n n n n n n n n n n n − Read, program, and erase operations from 2.7 to 3.6 V − Ideal for battery-powered applications

KM44C1000

Abstract: km44c1000bj KM44C1000BJ6 KM44C1000BP-7
Contextual Info: SAMSUNG ELECTRONICS INC L7E i 7^4142 DDISbHT B47 « S P I Ù K CMOS DRAM KM44C1000B 1 M x 4 Bit CMOS Dynamic RAM with Fast Page Mode FEATURES GENERAL DESCRIPTION • Performance range: The Samsung KM44C1000B is a high speed CMOS 1,048,516 x 4 Dynamic Random Access Memory. Its de­

L7251

Abstract: L7251 3.1
Contextual Info: MOTOROLA SC HEflOR Y / A S I C SfiE » b3fc.72Sl G D 6 7 1 6 2 TTb m » 0 J 3 MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM54100A MCM5L4100A Advance Information 4M x 1 CMOS Dynamic RAM Fast Page Mode The MCM54100A is a 0.7n CMOS high-speed dynamic random access memory. It is

Contextual Info: ADVANCE IC R O IM 512K WIDE DRAM X MT4C8512/3 S 8 WIDE DRAM 512K x 8 DRAM FEATURES • Industry-standard x8 pinouts, timing, functions and packages • Address entry: ten row-addresses, nine columnaddresses • High-performance CMOS silicon-gate process • Single +5V ±10% power supply

IGBT Battery 120 watt Charger circuit diagrams

Abstract: tl494 spice model four relay stabilizer circuit diagram 650 va gsm door lock circuit diagram MRC 433 mosfet MC34066 SOLUTION FOR SMPS USING TL494 MOSFET ESD Rated TL594 phone charger car power inverter TL494
Contextual Info: BRD8016/D Rev. 0, Nov-2000 Wireless Component Solutions for Handsets and Accessories Wireless Component Solutions for Handsets and Accessories BRD8016/D Rev. 0, Nov–2000  SCILLC, 2000 “All Rights Reserved’’ WIRELESS EZFET is a trademark of Semiconductor Components Industries, LLC SCILLC .

Contextual Info: niCRON S E M I C O N D U C T O R INC L3E D • b 1 1 1 5 14^ 0 0 0 7 71 S ATI ■ URN ADVANCE MICRON ■ 512K SEMICONDUCTOR. INC. WIDE DRAM X MT4C8512/3S 8 WIDE DRAM 512K x 8 DRAM FEATURES • Industry-standard x8 pinouts, timing, functions and packages • Address entry: ten row-addresses, nine columnaddresses

Contextual Info: Features • Single 2.7V - 3.6V Supply • Sequential Access, Parallel I/O Architecture • Page Program Operation - Single Cycle Reprogram Erase and Program - 4096 Pages (264 Bytes/Page) Main Memory • Two 264-Byte Data Buffers - Allows Receiving of Data while

c9013

Abstract: 84 pin PBGA oscilloscope MTBF TSMC retention memory dc 8069 IS61C1024 IC Data-book Q-16 car radio 14x20 TSOP 8638
Contextual Info: ISSI Integrated Silicon Solution, Inc. Quality and Reliability 1997-1998 An ISO 9001 Company ISSI ® Quality System Manual QUALITY Reliabilty Report 1997-1998 RELIABILITY Integrated Silicon Solution, Inc. An ISO 9001 Company 1997 Integrated Silicon Solution, Inc.

Contextual Info: À U ujüP M 1 \ 1 < » H Ili h! î Hc Li V-s 11 ( ; is i h - l i t f S !I ; H i l! i vj Advance information Features •A utom atic an d direct precharge 1 Burst read, single w rite • O rganization: 1 ,0 4 8 ,5 7 6 w ords x 8 bits x 2 banks (2M x8) 3 2 4 ,2 8 8 w ords x 16 bits x 2 banks

Contextual Info: Features • Single 2.7V - 3.6V Supply • Serial Interface Architecture • Page Program Operation - Single Cycle Reprogram Erase and Program - 1024 Pages (264 Bytes/Page) Main Memory • Two 264-Byte SRAM Data Buffers - Allows Receiving of Data while Reprogramming of Non-Volatile Memory

D0243

Contextual Info: FLASH MEMORY KM29V32000TS/RS 4M x 8 Bit NAND Flash Memory FEATURES GENERAL DESCRIPTION • Single 3.3 - volt Supply • Organization - Memory Celi Array : 4M +128K bit x 8bit - Data Register : (512 + 16)bit x 8bit • Automatic Program and Erase - Page Program : (512 + 16)Byte

d802 P nec

Abstract: D42S17805LG5-A60 358 ez 802 D42S17805LG5 d802 q nec ELF AMPLIFIER
Contextual Info: DATA SHEET NEC / MOS INTEGRATED CIRCUIT =_/ /zPD42S17805L, 4217805L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, HYPER PAGE MODE D e s c rip tio n The /iP D 42S 17805L, 4217805L are 2,097,152 words by 8 bits CMOS dynam ic RAMs with optional hyper page

Contextual Info: IN TEL CORP -CHEI10RY/PLD/ b7E ini^l D • 4fl2bl7b A M 9 @ ODfllSBO 405 g 28F016SA 16 MBIT 1 MBIT x 16, 2 MBIT x 8 FLASHFILE MEMORY ■ User-Selectable 3.3V or 5V V cc ■ ■ User-Configurable x8 or x16 Operation Command Execution — W rite During Erase

LE347

Abstract: toba Q 0265 R HS 8180 42S18180
Contextual Info: L427S2S DQ4 2 4 M4 b 70 • NECE MOS INTEGRATED CIRCUIT ju P D 4 2 S 1 6 1 8 0 ,4 2 S 1 7 1 8 0 ,4 2 S 1 8 1 8 0 16 M BIT D Y N A M IC RAM FAST PAGE M O D E & BYTE R E A D /W R IT E M ODE - P R E LIM IN A R Y -D ESCRIPTIO N

b427SES

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT >IEC MPD42S18165,4218165 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description The /j PD42S18165, 4218165 are 1 048 576 words by 16 bits CMOS dynam ic RAMs w ith optional hyper page

Contextual Info: Features • Single 4.5V - 5.5V Supply • Serial Interface Architecture • Page Program Operation - Single Cycle Reprogram Erase and Program - 2048 Pages (264 Bytes/Page) Main Memory • Two 264-Byte SRAM Data Buffers - Allows Receiving of Data while Reprogramming of