TS-42 RESET Search Results

Contextual Info: HPFC-5100, HPFC-5166 Tachyon TL and TS 42 PM Mass Storage Fibre Channel ICs PRODUCT OVERVIEW Released Product Brief :0 10 6 00 ,2 ch 66 MHz 3M ar • Loop Map, Loop Broadcast, Loop Directed Reset, and Loop Bypass Support • TL/TS is a Little Endian Device note that the PCI bus is Little Endian

PLESSEY CLA

Abstract: full adder circuit using nor gates Plessey PLESSEY CLA2000 CLA21XX CLA2000 SERIES plessey semi-custom
Contextual Info: PLESSEY SEMICONDUCTORS tS 7220513 PLESSEY SEMICONDUCTORS A PLESSEY w ' Semiconductors. Ï Ë| 7SH0S13 DODSSMfl 7 65C 05548 D /P ^ T-42-11-09 _CLA2000 series MICROGATE-C 1 CLA2000 SERIES Microgate-C is a semi-custom design technique for the production of gate arrays on Plessey Semiconductors high

Contextual Info: 42 PM PM2329 ClassiPI Network Classification Processor Datasheet te ep nd ay ,1 6S ClassiPI m be r, 20 07 10 :0 3: PM2329 Datasheet Proprietary and Confidential HS Pa r ts Ma na g em en tI nc .o fI HS IN C on Su Network Classification Processor by I Copyright 2005 PMC-SIerra, Inc. All rights reserved

ATV750-20DI

Abstract: V750L ATV750 ATV750L-30 ATV750-20DC
Contextual Info: ATV750/L Features • T hird G eneration Program m able Logic Structure H igh D e n sity Replacem ent fo r D iscrete L o g ic High Speed - Plus a New Low Power V ersion Increased L o g ic F le x ib ility 42 In p u ts an d 20 Sum te rm s Flexible O u tp u t L o g ic

STM32F101

Abstract: JTAG stm32f101 USART2 USART3 PC14-OSC32 PC13-ANTI MCBSTM32 MCBSTM32-v1.1 PC14-OSC32-IN PA13
Contextual Info: STM32F101-64 IC2 pA pB +3,3V t- JC 27 • PAO PA1 PAP PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 14 15 16 17 20 21 22 23 41 42 43 44 45 46 49 50 PAO/WKU P/U S A R T 2 C T S /A D C 0 /IT M 2 C H 1 PC0/ADC10 PA1 /U SA R T2R TS /AD C 1 /TI M 2 C H 2

CXD2311AR

Contextual Info: CXD2311AR 1/2 IL22 * C-MOS 10-BIT 20MSPS VIDEO A/D CONVERTER 25 40 PIN I/O NO. 1 2 3 4 5 6 7 8 9 10 11 12 SIGNAL O O O O O — — O O O O O INPUT CAL CE CLK LINV MINV OE RESET SEL TESTMODE TIN TS TSTR V IN VRB VRT D0 D1 D2 D3 D4 DGND DVDD D5 D6

Contextual Info: IC for CMOS System Reset PST4XXAXXXN MITSUMI IC for CMOS System Reset Monolithic IC PST4XXAXXXN Series Outline This is a system reset IC developed using the CMOS process. The CMOS process allows ultra-low current consumption of 1.5µA typ. . Further, a fixed delay timer is built in, so that supply voltage is verified when the

LSI2032

Abstract: SBC5206 74FCT16245 MCM32 VinC26 27C080 D24-D25 pd446 J42C27 TL7705ACP
Contextual Info: SP7 9x4.7K +5 1 +5 SP4 2 3 4 5 6 7 8 910 9x4.7K +5 1 A[0.27] 2 3 4 5 6 7 8 910 160150 140128118110 102 94 86 77 6960 52 44 36 3024 1812 59 -RESET 62 63 64 -IRQ7 -IRQ4 -IRQ1 66 67 68 -BR -BD -BG 127 126 125 121 122 124 -BKPT DSI -HIZ DSCLK TCK DSO 159 158

LP3J

Contextual Info: ASSESS? CD74HC161, CD74HCT161, CD74HC163, CD74HCT163 High Speed CM OS Logic Presettable Counters February 1998 Features Description • CD74HC161, CD74HCT161 4-Bit Binary Counter, Asynchronous Reset The Harris CD74HC161, CD74HCT161, CD74HC163 and CD74HCT163 are presettable synchronous counters that

MRAB

Abstract: 74ABT161543 74ABTH161543 8EN10 BT161543DGG BT161543DL
Contextual Info: INTEGRATED CIRCUITS 74ABT161543 74ABTH161543 16-bit latched transceiver with dual enable and master reset 3-State Product specification Supersedes data of 1995 Sep 18 IC23 Data Handbook Philips Semiconductors 1998 Feb 27 Philips Semiconductors Product specification

Contextual Info: INTEGRATED CIRCUITS 74ABT161543 74ABTH161543 16-bit latched transceiver with dual enable and master reset 3-State Product specification Supersedes data of 1995 Sep 18 IC23 Data Handbook Philips Semiconductors 1998 Feb 27 Philips Semiconductors Product specification

Contextual Info: W E N SMD 5 x 20 S U R FA C E M O U N T I N G M I N I AT U R E F U S E - L I N K S O B E R F L Ä C H E N M O N TA G E G-SICHERUNGSEINSÄTZE SMD-FUSES / SMD-SICHERUNGEN NON RESETTABLE / NICHT RÜCKSTELLEND Miniature fuse-links Type SMD-FST 5‫ן‬20 G-Sicherungseinsätze

74ABT16823A

Abstract: 74ABT16823ADGG 74ABT16823ADL SSOP56 TSSOP56 diode 1d8
Contextual Info: INTEGRATED CIRCUITS 74ABT16823A 18-bit bus interface D-type flip-flop with reset and enable 3-State Product data Replaces data sheet 74ABT16823A/ABTH16823A of 1998 Feb 27 Philips Semiconductors 2004 Feb 02 Philips Semiconductors Product data 18-bit bus-interface D-type flip-flop

cd74hc161

Contextual Info: H A F R F R IS C D 7 4 H C 1 6 1 , C D 7 4 H C T 1 6 1 , SEMI CONDUCTOR C D 7 4 H C 1 6 3 , High Speed CMOS Logic Presettable Counters February 1998 Features • C D 7 4 H C T 1 6 3 Description CD74HC161, CD74HCT161 4-B it Binary Counter, Asynchronous Reset

U5020M

Abstract: U5020M-MFPG3Y U5020M-MFPY
Contextual Info: Features • • • • • • • • • Low Current Consumption: IDD < 100 µA RC Oscillator Internal Reset During Power-up and Supply Voltage Drops POR “Short” Trigger Window for Active Mode “Long” Trigger Window for Sleep Mode Cyclical Wake-up of the Microcontroller in Sleep Mode

74ABT16823A

Abstract: 74ABTH16823A BT16823ADL MSA400
Contextual Info: Philips Semiconductors Product specification 18-bit bus-interface D-type flip-flop with reset and enable 3-State 74ABT16823A 74ABTH16823A FEATURES DESCRIPTION • Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops The 74ABT16823A 18-bit bus interface register is designed to

Contextual Info: M M O T O R O L A M ilita ry 54LS 162A 4 -B it D ecade C o u n ter (w ith Synchronous Clear) ELECTRICALLY TESTED PER: MIL-M-38510/31511 The 'LS162A is a high-speed 4 -b it syn ch ro n o u s coun ter. It is edgetrig g e re d , syn ch ro n o u sly p resettable, and cascadable MSI b u ild in g

74HCT175

Contextual Info: .Technical Data File N um b er 1474 CD54/74HC175 CD54/74HCT175 High-Speed CMOS Logic Quad D Flip-Flop with Reset Type Features: • m ■ m ■ C om m on C lock and A synchronous Reset on fo u r D- Type Flip-Flops Positive-edge pulse triggering C om plem entary Outputs

Contextual Info: LS TTL DN74LS Series DN74LS192 D N 7 4 L S 1 9 2 Synchronous BCD U p/D ow n Dual Clock Counters with Reset • Description DN74LS192 is a synchronous decade up/down counter with direct-coupled reset input and set input. P -2 ■ Features • • • •

A250

Contextual Info: FUSES / SICHERUNGEN Non resettable fuses / Nicht rückstellende Sicherungen Geräteschutzsicherungen Typ 172600 time-delay TD high breaking capacity Ceramic tube träge TD grosses Ausschaltvermögen Keramikrohr 50 75 Pre-arcing time in seconds ts Schmelzzeit in Sekunden ts

74ALVCH16823

Abstract: SSOP56 TSSOP56
Contextual Info: Philips Semiconductors Product specification 7AA. xrnu. aar o 18-bit bus-interface D-type flip-flop with reset and enable 3-State) 74ALVCH16823 FEATURES DESCRIPTION • W id e s u p p ly v o lta g e ra n g e o f 1 .2 V to 3.6 V T h e 7 4 A L V C H 1 6 8 2 3 is a 18 -bit e d g e -trig g e re d flip -flo p fe a tu rin g

cehess fuses ceramic

Abstract: CEHESS cehess fuses UNA250 A250
Contextual Info: FUSES / SICHERUNGEN NON RESETTABLE / NICHT RÜCKSTELLEND G-Sicherungseinsätze Typ 172 600 super-time-lag TT high breaking capacity Ceramic tube superträge TT grosses Ausschaltvermögen Keramikrohr 50 75 Pre-arcing time in seconds ts Schmelzzeit in Sekunden ts

Contextual Info: 4044B QUAD R /S LATCH WITH 3-STATE OUTPUTS D E S C R IP TIO N — The 4044B is a Quad R/S Latch w ith 3-state O utpu ts w ith a com m o n O u tp u t Enable In p u t EO . Each latch has an active LO W Set In p u t (Sn ), an active LO W Reset In p u t (R n ) and

HD74LS90

Contextual Info: •D ecade Counters The H D 74LS90 contains four master-slave flip-flops and addi­ IBLOCK DIAGRAM tional gating to provide a divide-by-two counter and threestage binary counter for divide-by-five. This device has a gated zero reset and also has gated set-to-nine inputs for use in BCD