TPHL13 Search Results

CDC318

Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

kinta x

Abstract: F667 1N3064 int1200 L55 TRANSMITTER DIODE
Contextual Info: MI L-M-3 85 10 /48 1A U SA F 18 June 1984_ SUPERSEDING MI L-M-3 85 10 /48 1Î US AF) 28 F e b r u a r y 1982 QUAL I FI CATI ON REQUIREMENTS REMOVED M I L I T A RY S P E C I F I C A T I O N M I C R O C I R C U I T S , D I G I T A L , N-CHANNEL, S I L I C O N GATE

Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

48-PIN

Abstract: CDC318A CDC318ADL CDC318ADLG4
Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications

daq 6008

Abstract: AM2901C/BQA ABAZ Mostek 6008 2901c AM2901c-BYC PHL22 F0736 UI5 321
Contextual Info: D E S C FORM 193 MAY B6 This Material Copyrighted By Its Respective Manufacturer ± 1. SCOPE 1.1 Scope. T h is drawing d e scrio e s d evice renuirem ents fo r c la s s B m ic r o c ir c u it s in accordance with

48-PIN

Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications

K3638

Abstract: 4Y04
Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications

Contextual Info: M MOTOROLA Military 54LS181 4-Bit Arithmetic Logic Unit MPO mini ELECTRICALLY TESTED PER: MIL-M-35810/30801 T h e 54LS181 is a 4 -b it A rith m etic L ogic U nit (ALU ) w hich can perform all th e possib le 16 logic o pe ra tio ns on tw o va ria b le s and a v a rie ty of

48-PIN

Abstract: CDC318A
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications

marking code ADg

Abstract: ic 76 adg l7 723 M/A relay lzl T7895 aos Lot Code Identification n7t marking iwatt marking
Contextual Info: MIL-M-38510/520B 20 JUNE 1983 W L R S E DING-MIL-M-38510/520A 9 D e c e m b e r 1982 MILITARY MICROCIRCUITS, SPECIFICATION DIGITAL, MONOLITHIC N-CHANNEL, SILICON GATE 16-BIT M I C R O PR OC ES SO R T h i s s p e c i f i c a t i o n is a p p r o v e d f o r u s e b y all D e p a r t ­

k3638

Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications

CDC318

Abstract: CDC318DL CDC318DLR
Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

Contextual Info: M M O T O R O L A M ilita ry 54ALS161 Synchronous 4-Bit Binary Counter (With Asynchronous Clear) ELECTRICALLY TESTED PER: MPG54ALS161 AVAILABLE AS: The ALS161 is a high-speed 4-bit synchronous counter. It is edgetriggered, synchronously presetable, and cascadable MSI building

hl43

Abstract: TIL413 IZ6 data sheet PJ 3139 B38G 2901c marking AYB
Contextual Info: I QUALI FI CAI 1ÜTTI I REQUIREMENTS I REMOVED M I I MILITARY MICROCIRCUITS, DIGITAL, T h i s s p e c i f i c a t i o n is ments and Agencies should be FOUR-31T noted that previous MICROPROCESSOR Scope. This reflected approved of the f o r u s e by Department

CDIP2-T20

Abstract: icc 312 106aa
Contextual Info: INCH-POUND MIL-M-38510/338B 10 February 2004 SUPERSEDING MIL-M-38510/338A 22 May 1990 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, ARITHMETIC LOGIC UNITS, MONOLITHIC SILICON Reactivated after 10 February 2004 and may be used for either new or existing design acquisition.

smlx

Abstract: 2901c ABAZ daq 6008 phl40 LH27
Contextual Info: D E S C FORM 193 MAY B6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 ± 1. SCOPE 1.1 Scope. This drawing descrioes device renuirements fo r c la s s B m icro circu its in accordance with

Contextual Info: CDC318A l-LINE TO 18-LINE CLOCK DRIVER WITH |2C CONTROL INTERFACE SC AS 614 - SE P TE M B E R 1998 High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM SDRAM Clock Buffering Applications Output Skew, tSk(0), Less Than 250 ps Pulse Skew, tSk(P), Less Than 500 ps

6358NS

Contextual Info: M Military 54LS192 M O TO R O LA Presettable BCD/Decade UP/Down Counter ELECTRICALLY TESTED PER: MIL-M-38510/31507 M U HM The 54LS192 is an UP/DOWN BCD Decade (8421) Counter and the 54LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the

Contextual Info: Ordering number:ENN3029B Monolithic Digital IC LB8902M 3-Channel Clock Driver Overview Package Dimensions • The LB8902M is designed to drive a capacitive load at a high speed. • Suited for horizontal clock drive of CCD image sensor. unit:mm 3097A-MFP16FS

8300102qx

Abstract: phl24
Contextual Info: iD I S T R I B y T I O N S T A T E M E N T iA i_ A p p ro v e d fo r p u b lic re le a se ; d is tr ib u tio n is u n lim ite d . DESC FORM 193 MAY 86 1. SCOPE 1.1 Scope. T h is draw ing d e s c rib e s d e v ic e re q u ire m e n ts f o r c la s s B m ic r o c ir c u i t s in acco rdan ce

CDFP2-F14 DIMENSIONS

Contextual Info: INCH-POUND MIL-M-38510/315D 27 October 2003 SUPERSEDING MIL-M-38510/315C 17 JANUARY 1984 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, LOW-POWER SCHOTTKY TTL, COUNTERS, MONOLITHIC SILICON Inactive for new design after 18 April 1997. This specification is approved for use by all Departments

Contextual Info: M MOTOROLA Military 54LS181 4-Bit Arithmetic Logic Unit ELECTRICALLY TESTED PER: MIL-M-35810/30801 H P O /////// T h e 54LS181 is a 4 -b it A rith m e tic Logic U nit (ALU ) w hich can perform all th e p ossib le 16 logic o pe ra tion s on tw o va ria b le s and a va rie ty of

Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications

Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Add device type 02. Add packages J and 3 for device type 02. Editorial changes throughout. 93-02-16 Monica L. Poelking B Update to current requirements. Editorial changes throughout. - gap 06-01-05 Raymond Monnin