TPHL12 Search Results

ADuM1250

Abstract: MS-012-AA PWD21
Contextual Info: Hot Swappable, Dual I2C Isolators ADuM1250/ADuM1251 FUNCTIONAL BLOCK DIAGRAMS VDD1 1 DECODE ENCODE 8 VDD2 SDA1 2 ENCODE DECODE 7 SDA2 SCL1 3 DECODE ENCODE 6 SCL2 GND1 4 ENCODE DECODE 5 GND2 Figure 1. ADuM1250 VDD1 1 DECODE ENCODE 8 VDD2 SDA1 2 ENCODE DECODE

CDC318

Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

kinta x

Abstract: F667 1N3064 int1200 L55 TRANSMITTER DIODE
Contextual Info: MI L-M-3 85 10 /48 1A U SA F 18 June 1984_ SUPERSEDING MI L-M-3 85 10 /48 1Î US AF) 28 F e b r u a r y 1982 QUAL I FI CATI ON REQUIREMENTS REMOVED M I L I T A RY S P E C I F I C A T I O N M I C R O C I R C U I T S , D I G I T A L , N-CHANNEL, S I L I C O N GATE

3014 LED

Abstract: MARKING CFK l1801-1 SVI 3003 W2T marking 103 c1k end of life car tyres T-17911 54ls162 jill2
Contextual Info: MIL-M-38510/315C 17 Ja n u a r y 1984 SUPERSEDING M I L - M - 3 8 5 1 0 / 3 1 5B 16 April 1981 MILITARY MICROCIRCUITS, SPECIFICATION DIGITAL, T T L , COUNTERS, LOW-POWER MONOLITHIC T hi s s p e c i f i c a t i o n is a p p r o v e d ments and Agencies of th e

80c85

Abstract: HS80C85
Contextual Info: S H S - 5 4 C 1 3 8 R H R a d ia t io n H a r d e n e d February 1996 3 - L in e to 8 - L in e D e c o d e r /D e m u lt ip le x e r Features Pinouts • Devices QML Qualified in Accordance With MIL-PRF-38535 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP

sidd

Abstract: SA2995 Harris top marking
Contextual Info: 33 fcKHffiSR HS-54C138RH Radiation Hardened 3-Line to 8-Line Decoder/Demultiplexer December 1992 Pinouts Features 16 PIN DIP CASE OUTLINE D2, CONFIGURATION 3 TOP VIEW • Radiation Hardened EPI-CMOS - Total Dose 1 x 10s RAD Si - Latch-Up Immune > 1 x 1012 RAD(Si)/s

Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

48-PIN

Abstract: CDC318A CDC318ADL CDC318ADLG4
Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications

E1140

Abstract: military part marking symbols serial number z0844204
Contextual Info: REVISIONS LTR DATE YR-MO-DA DESCRIPTIO N Change V i m , VjH2> and tpHL]3. 1985 Jan 2 Change end-point electrical test requirements in table II. Extensive changes to table I. Editorial changes throughout. 1986 Apr 14 Change to military drawing format. Changes to table I.

RH-1750

Abstract: RH1750 qml-38535 PLH23 PHL27
Contextual Info: REVISIONS LTR DESCRIPTION DATE APPROVED YR-MO-DA REV SHEET REV SHEET 15 16 17 REV STATUS OF SHEETS PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE 18 19 20 21 22 23 24

2901C

Contextual Info: _D J^ T R IB U T IO N S T A T E M E N T A ^ Approved for public re le a se ; distribution is unlim ited. DESC FORM 193 MAY B6 1. SCOPE 1.1 Scope. T h is drawing d e scrio e s d evice requirem ents fo r c la s s B m ic r o c ir c u it s in accordance with 1 .2 .1 o f MlL-STD-883, “P ro v isio n s fo r the use o f MIL-STD-883 in co n ju n ctio n w ith com pliant non-JAN

Contextual Info: Hot Swappable, Dual I2C Isolators ADuM1250/ADuM1251 Data Sheet APPLICATIONS VDD1 1 DECODE ENCODE 8 VDD2 SDA1 2 ENCODE DECODE 7 SDA2 SCL1 3 DECODE ENCODE 6 SCL2 GND1 4 ENCODE DECODE 5 GND2 06113-001 FUNCTIONAL BLOCK DIAGRAMS Bidirectional I2C communication

Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM isoPower integrated, isolated dc-to-dc converter Regulated 3.15 V to 5.25 V output Up to 150 mW output power High common-mode transient immunity: >25 kV/µs iCoupler integrated I2C digital isolator Bidirectional I2C communication

48-PIN

Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications

ADUM1250ARZ

Abstract: PWD21 adum1250
Contextual Info: Hot Swappable Dual I2C Isolators ADuM1250/ADuM1251 APPLICATIONS 2 Isolated I C, SMBus, or PMBus interfaces Multilevel I2C interfaces Power supplies Networking Power-over-Ethernet FUNCTIONAL BLOCK DIAGRAMS VDD1 1 DECODE ENCODE 8 VDD2 SDA1 2 ENCODE DECODE 7

Contextual Info: HS-54C138RH S em iconductor Radiation Hardened 3-Line to 8-Line Decoder/Demultiplexer February 1996 Pinouts Features • Devices QML Qualified in Accordance With MIL-PRF-38535 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T16 • Detailed Electrical and Screening Requirements are

IS1540

Abstract: IS1541 IS154
Contextual Info: ISO1540 ISO1541 www.ti.com SLLSEB6B – JULY 2012 – REVISED MAY 2013 Low-Power Bidirectional I2C Isolators Check for Samples: ISO1540, ISO1541 • • • • • • Isolated Bidirectional, I C Compatible, Communications Supports up to 1 MHz Operation 3-V to 5.5-V Supply Range

Contextual Info: M MOTOROLA Military 54F181 Advance Information 4-B it A rith m e tic L o g ic U n it ELECTRICALLY TESTED PER: MPG54F181 The 54F181 is a 4 -b it A rith m e tic Logic U n it (ALU) w h ic h can p e rfo rm all th e possib le 16 log ic o p e ra tio n s on tw o va ria b le s and a v a rie ty o f

K3638

Abstract: 4Y04
Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications

Contextual Info: M MOTOROLA Military 54LS181 4-Bit Arithmetic Logic Unit MPO mini ELECTRICALLY TESTED PER: MIL-M-35810/30801 T h e 54LS181 is a 4 -b it A rith m etic L ogic U nit (ALU ) w hich can perform all th e possib le 16 logic o pe ra tio ns on tw o va ria b le s and a v a rie ty of

Contextual Info: ISO1540 ISO1541 www.ti.com SLLSEB6A – JULY 2012 – REVISED OCTOBER 2012 Low-Power Bidirectional I2C Isolators Check for Samples: ISO1540, ISO1541 • • • • • • Isolated Bidirectional, I C Compatible, Communications Supports up to 1 MHz Operation

48-PIN

Abstract: CDC318A
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications

54ALS161

Contextual Info: REVISIONS C Change VJL, tp clock , fflAX, and propagation delay limits. Delete minimum limits from IJL and propagation delays. Convert to military drawing format. Case E inactive for new design D Change drawing CAGE number to 67268. Change IJL condition. Change tpLH2 - Correct vendor p/n. Case 2, device types 01 and

QML-38535

Abstract: GDIP4-T28 smd "vhz"
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED REV SHEET REV SHEET 15 16 17 REV STATUS OF SHEETS PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A 18 19 20 21