TPHL14 Search Results

SCANSTA111

Abstract: STA111
Contextual Info: SCANSTA111 Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 JTAG Port General Description The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board

CDC318

Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

48-PIN

Abstract: CDC318A CDC318ADL CDC318ADLG4
Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications

Contextual Info: SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 JTAG Port Check for Samples: SCANSTA111 FEATURES DESCRIPTION • The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The

Contextual Info: SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 JTAG Port Check for Samples: SCANSTA111 FEATURES DESCRIPTION • The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The

48-PIN

Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications

K3638

Abstract: 4Y04
Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications

48-PIN

Abstract: CDC318A
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications

marking code ADg

Abstract: ic 76 adg l7 723 M/A relay lzl T7895 aos Lot Code Identification n7t marking iwatt marking
Contextual Info: MIL-M-38510/520B 20 JUNE 1983 W L R S E DING-MIL-M-38510/520A 9 D e c e m b e r 1982 MILITARY MICROCIRCUITS, SPECIFICATION DIGITAL, MONOLITHIC N-CHANNEL, SILICON GATE 16-BIT M I C R O PR OC ES SO R T h i s s p e c i f i c a t i o n is a p p r o v e d f o r u s e b y all D e p a r t ­

STA111

Abstract: SCANSTA111
Contextual Info: SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 JTAG Port • Mode Register0 allows local TAPs to be bypassed, General Description The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved

k3638

Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications

CDC318

Abstract: CDC318DL CDC318DLR
Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

Contextual Info: M M O T O R O L A M ilita ry 54LS191 Synchronous 4-B it Up/Down B inary Counter W ith M ode Control ELECTRICALLY TESTED PER: MIL-M-38510/31509 M T h e 54LS191 is a syn ch ro n o u s U P/D O W N M odu lo -16 B inary C ounter. S tate ch a n g e s o f th e co un ters are syn chro n o us w ith the

CDC318

Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

CDIP2-T20

Abstract: icc 312 106aa
Contextual Info: INCH-POUND MIL-M-38510/338B 10 February 2004 SUPERSEDING MIL-M-38510/338A 22 May 1990 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, ARITHMETIC LOGIC UNITS, MONOLITHIC SILICON Reactivated after 10 February 2004 and may be used for either new or existing design acquisition.

Contextual Info: M M O T O R O L A M ilitary 54LS191 Synchronous 4-Bit Up/Down Binary Counter With Mode Control ELECTRICALLY TESTED PER: MIL-M-38510/31509 M T h e 54LS191 is a syn ch ro n o u s U P/D O W N M o du lo -16 Binary C ounter. S ta te ch a n g e s of the co un ters are syn chro n o us w ith the

Contextual Info: CDC318A l-LINE TO 18-LINE CLOCK DRIVER WITH |2C CONTROL INTERFACE SC AS 614 - SE P TE M B E R 1998 High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM SDRAM Clock Buffering Applications Output Skew, tSk(0), Less Than 250 ps Pulse Skew, tSk(P), Less Than 500 ps

Contextual Info: CDC222 1-LINE TO 15-LINE DIFFERENTIAL CLOCK DRIVER S C A S 5 4 8 A - NOVEMBER 1995 - REVISED JUNE 1996 Low Output Skew for Clock-Dlstrlbutlon and Clock-Generatlon Applications Output Reference Voltage, V r e r Allows Distribution From a Single-Ended Clock

6358NS

Contextual Info: M Military 54LS192 M O TO R O LA Presettable BCD/Decade UP/Down Counter ELECTRICALLY TESTED PER: MIL-M-38510/31507 M U HM The 54LS192 is an UP/DOWN BCD Decade (8421) Counter and the 54LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the

AA1010

Abstract: SCANSTA111 STA111
Contextual Info: SCANSTA111 Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 JTAG Port General Description The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board

BL 55076

Abstract: 4525 GE 52033 LTWU wto Iran 8086 microprocessor based project 35502 42802 s8510 stt-11
Contextual Info: M I L - M - 385 10/5 3 0 U S A F 10 November 1980 MILITARY MICROCIRCUITS, M O N O LI T H I C S P E CI F I C A T I O N DIGITAL, N-CHA N N E L , 16-BIT M I C R O P R O C E S S O R S I L I C O N GATE (FIXED INSTR U C T I O N ) This s p e c i f i c a t i o n is a p p ro v e d for use by R o m e A i r D e v e l o p m e n t

CDFP2-F14 DIMENSIONS

Contextual Info: INCH-POUND MIL-M-38510/315D 27 October 2003 SUPERSEDING MIL-M-38510/315C 17 JANUARY 1984 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, LOW-POWER SCHOTTKY TTL, COUNTERS, MONOLITHIC SILICON Inactive for new design after 18 April 1997. This specification is approved for use by all Departments

Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications