TPD 5000 Search Results

7400series

Abstract: cmos logic 7400 series 7400 family TTL 7400-series EPM5016
Contextual Info: The Complete Industry-Standard Programm able Logic Family MAX 5000 EPLDs 384 EPM5192 tpp = 25 ns - C/> 0> .c o 3 08 EPM5128 tpp —25 ns 256 CO Q. A EPM5130 tpp —25 ns O / ca> D EPM5064, tPD = 25 ns 128 ▲ EPM5032, tPD = 15 ns 64 ▲ EPM5016, tPD = 15 ns

Contextual Info: fax id: 5000 ss ^ |>»r ^ " L CY101E383 1f~~* ]L~|_? ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 2.5 ns tpD TTL-to-ECL — 3 ns tpD ECL-to-TTL • • • • • • • • • •

E383

Abstract: all ttl family not ecl quad single supply 50 Ohm Line Drivers TTL LOGIC DATA BOOK CY101E383 R2170 E3836 E3834 E3831
Contextual Info: fax id: 5000 1CY 101 E3 83 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL • • • • • • • • • • — 4 ns tPD ECL-to-TTL Low skew < ± 1 ns

Contextual Info: fax id: 5000 «f C Y 101E383 c y pr es s ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tpD TTL-to-ECL — 4 ns tpD ECL-to-TTL Low skew < ± 1 ns Can operate on single +5V supply

STG3685

Abstract: STG3685BJR
Contextual Info: STG3685 LOW VOLTAGE 0.5Ω MAX DUAL SPDT SWITCH, SINGLE ENABLE WITH BREAK BEFORE MAKE FEATURE PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 0.3ns TYP. at VCC = 3.0V tPD = 0.4ns (TYP.) at VCC = 2.3V ULTRA LOW POWER DISSIPATION: ICC = 0.2µA (MAX.) at TA = 85°C

STG3685

Abstract: STG3685BJR
Contextual Info: STG3685 LOW VOLTAGE 0.5Ω MAX DUAL SPDT SWITCH, SINGLE ENABLE WITH BREAK BEFORE MAKE FEATURE PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 0.3ns TYP. at VCC = 3.0V tPD = 0.4ns (TYP.) at VCC = 2.3V ULTRA LOW POWER DISSIPATION: ICC = 0.2µA (MAX.) at TA = 85°C

STG3685

Abstract: STG3685BJR
Contextual Info: STG3685 LOW VOLTAGE 0.5Ω MAX DUAL SPDT SWITCH, SINGLE ENABLE WITH BREAK BEFORE MAKE FEATURE PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 0.3ns TYP. at VCC = 3.0V tPD = 0.4ns (TYP.) at VCC = 2.3V ULTRA LOW POWER DISSIPATION: ICC = 0.2µA (MAX.) at TA = 85°C

Contextual Info: Macro-Embedded Type Celt Arrays • CE46 Series Features High integration: Technology: Gate delay time: Maximum 198,084 BCs on chip Si-gate CMOS, 2-layer metal Standard gate tpd=360 ps (2-input NAND, standard load, V dd=5 V) tpd=520 ps (2-input NAND, standard load, V dd=3.3 V)

22V10 PAL CMOS device

Abstract: lv- 28p MACH446 vantis PAL 22V10 M4-256/128 mach355 M5A3-512 MACH111 12JC 14JI MACH221SP-10 palce22v10h-10
Contextual Info: Overview Vantis Device Selector Guide MACH 4 FAMILY Table 1. MACH 4 Devices1 Commercial Ind’l 2 tPD ns fCNT MHz tPD ns 7.5 111.1 10 5.5 5.5 10 95.2 12 6 6.5 12 76.9 14 7 8 15 55.6 18 10 10 7.5 111.1 10 5.5 5.5 10 95.2 12 6 6.5 12 76.9 14 7 8 M4 LV -64/32-15

EPM5130

Abstract: D1398
Contextual Info: EPM 5130 EPLD High-density, 128-macrocell, general-purpose MAX 5000 EPLD 128 macrocells optimized for pin-intensive applications, easily integrating over 60 TTL MSI and SSI components High-speed multi-LAB architecture tPD as fast as 15 ns Counter frequencies up to 83.3 MHz

Contextual Info: EPM5032 EPLD □ Features □ □ □ □ General Description High-speed 28-pin DIP, J-lead, or SOIC single-LAB MAX 5000 EPLD Combinatorial speeds with tPD = 15 ns Counter frequencies up to 76 MHz Pipelined data rates up to 83 MHz 32 individually configurable macrocells

7400 series TTL pinouts

Abstract: EPLD 5128
Contextual Info: EPM 5128 EPLD Features □ □ High-density 128-macrocell general-purpose M AX 5000 EPLD 256 shareable expander product terms that allow over 32 product terms in a single macrocell High-speed multi-LAB architecture tPD as fast as 25 ns Counter frequencies up to 50 MHz

Contextual Info: Features • ■ ■ ■ ■ ■ ■ High-density, 64-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture tpD as fast as 15 ns Counter frequencies up to 83.3 MHz Pipelined data rates up to 100 MHz 128 shareable expander product terms "expanders" allowing over

EPM5064

Abstract: EPM5064-1
Contextual Info: EPM5064 EPLD Features □ □ □ □ □ □ High-density, 64-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture tPD as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 63 MHz 128 shareable expander product terms "expanders" allowing over

ALTERA MAX 5000 programming

Contextual Info: EPM 5016 EPLD Features □ □ □ □ □ □ High-speed, single-LAB M AX 5000 EPLD tPD as fast as 15 ns Counter frequencies up to 100 MHz Pipelined data rates up to 100 MHz 16 individually configurable macrocells 32 shareable expander product terms "expand ers" allow ing 36

EPM5016

Abstract: EPMS016
Contextual Info: EPM5016 EPLD Features □ □ □ □ □ □ □ □ General Description High-speed 20-pin DIP, J-lead, or SOIC single-LAB MAX 5000 EPLD Combinatorial speeds with tPD = 15 ns Counter frequencies up to 100 MHz Pipelined data rates up to 100 MHz 16 individually configurable macrocells

EPM7256

Contextual Info: EPM7256 EPLD High-Performance 256-Macrocell Device Data Sheet September 1992, ver. 2 □ Features. High-density, erasable CMOS EPLD based on second-generation Multiple Array Matrix MAX architecture 5,000 usable gates Combinatorial speeds with tPD = 20 ns

F1H16

Abstract: EPM 5192 epm5192 MSI MS-5 IC LM 384 gn
Contextual Info: EPM 5192 EPLD F e a tu re s • High-density, 192 macrocell, general-purpose M AX 5000 EPLD, easily integrating com plete logic boards into a single package High-speed m ulti-LAB architecture tpD as fast as 15 ns Counter frequencies up to 83.3 MHz Pipelined data rates up to 100 MHz

Contextual Info: SN54HC257, SN54HC258, SN74HC257, SN74HC258 QUADRUPLE 2ĆLINE TO 1ĆLINE DATA SELECTORS/MULTIPLEXERS WITH 3ĆSTATE OUTPUTS SCLS224B − DECEMBER 1982 − REVISED SEPTEMBER 2003 15 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D ’HC257 . . . Typical tpd = 9 ns

Contextual Info: 74AUP1G59 TinyLogic Low Power Universal Configurable Two-Input Logic Gate Open Drain Output Features Description • • 0.8V to 3.6V VCC Supply Operation  Extremely High Speed tPD - 3.2ns: Typical at 3.3V   Power-Off High-Impedance Inputs and Outputs

Contextual Info: MULTILEVEL PIPELINE REGISTERS IDT29FCT520AT/BT/CT/DT IDT29FCT521AT/BT/CT/DT Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Fastest CMOS logic family available • A, B, C and D speed grades with 5.2ns tPD • Available in DIP, SOIC, SSOP, CERPACK and LCC

Contextual Info: COM’L: -7.5 Î1 MACH210A-7 Advanced Micro Devices High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins 32 Outputs ■ 64 Macrocells 64 Flip-flops; 2 clock choices ■ 7.5 ns 4 “PAL22V16” blocks with buried macrocells ■ tpD

Contextual Info: EPM7096 EPLD Ü^ R*A\ High-Performance 96-Macrocell Device Data Sheet September 1992, ver. 2 Features □ High-density, erasable CMOS EPLD based on second-generation Multiple Array MatriX MAX architecture 1,800 usable gates Combinatorial speeds w ith tPD = 15 ns

XNOR FAIRCHILD

Abstract: IGBT DRIVER SCHEMATIC 3 PHASE 74AUP1G57 74AUP1G57FHX 74AUP1G57L6X JESD22-A114 XNOR 74 xnor
Contextual Info: 74AUP1G57 TinyLogic Low Power Universal Configurable TwoInput Logic Gate Features Description ƒ ƒ 0.8V to 3.6V VCC Supply Operation ƒ High Speed tPD - 2.9ns: Typical at 3.3V ƒ ƒ Power-Off High-Impedance Inputs and Outputs The 74AUP1G57 is a universal configurable 2-input