TPD 5000 Search Results

7400series

Abstract: cmos logic 7400 series 7400 family TTL 7400-series EPM5016
Contextual Info: The Complete Industry-Standard Programm able Logic Family MAX 5000 EPLDs 384 EPM5192 tpp = 25 ns - C/> 0> .c o 3 08 EPM5128 tpp —25 ns 256 CO Q. A EPM5130 tpp —25 ns O / ca> D EPM5064, tPD = 25 ns 128 ▲ EPM5032, tPD = 15 ns 64 ▲ EPM5016, tPD = 15 ns

E383

Abstract: all ttl family not ecl quad single supply 50 Ohm Line Drivers TTL LOGIC DATA BOOK CY101E383 R2170 E3836 E3834 E3831
Contextual Info: fax id: 5000 1CY 101 E3 83 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL • • • • • • • • • • — 4 ns tPD ECL-to-TTL Low skew < ± 1 ns

Contextual Info: fax id: 5000 «f C Y 101E383 c y pr es s ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tpD TTL-to-ECL — 4 ns tpD ECL-to-TTL Low skew < ± 1 ns Can operate on single +5V supply

STG3685

Abstract: STG3685BJR
Contextual Info: STG3685 LOW VOLTAGE 0.5Ω MAX DUAL SPDT SWITCH, SINGLE ENABLE WITH BREAK BEFORE MAKE FEATURE PRELIMINARY DATA • ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 0.3ns TYP. at VCC = 3.0V tPD = 0.4ns (TYP.) at VCC = 2.3V ULTRA LOW POWER DISSIPATION: ICC = 0.2µA (MAX.) at TA = 85°C

Contextual Info: Features • ■ ■ ■ ■ ■ ■ High-density, 64-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture tpD as fast as 15 ns Counter frequencies up to 83.3 MHz Pipelined data rates up to 100 MHz 128 shareable expander product terms "expanders" allowing over

EPM5064

Abstract: EPM5064-1
Contextual Info: EPM5064 EPLD Features □ □ □ □ □ □ High-density, 64-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture tPD as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 63 MHz 128 shareable expander product terms "expanders" allowing over

Altera EPM5128

Abstract: KX-K 8.0 MHz
Contextual Info: EPM 5128 EPLD Features • ■ High-density, 128-m acrocell, general-purpose MAX 5000 EPLD High-speed m ulti-LAB architecture tpD as fast as 15 ns Counter frequencies up to 83.3 MHz Pipelined data rates up to 100 MHz 256 shareable expander product terms “expanders" allow ing over

ALTERA MAX 5000 programming

Contextual Info: EPM 5016 EPLD Features □ □ □ □ □ □ High-speed, single-LAB M AX 5000 EPLD tPD as fast as 15 ns Counter frequencies up to 100 MHz Pipelined data rates up to 100 MHz 16 individually configurable macrocells 32 shareable expander product terms "expand ers" allow ing 36

EPM5016

Abstract: EPMS016
Contextual Info: EPM5016 EPLD Features □ □ □ □ □ □ □ □ General Description High-speed 20-pin DIP, J-lead, or SOIC single-LAB MAX 5000 EPLD Combinatorial speeds with tPD = 15 ns Counter frequencies up to 100 MHz Pipelined data rates up to 100 MHz 16 individually configurable macrocells

F1H16

Abstract: EPM 5192 epm5192 MSI MS-5 IC LM 384 gn
Contextual Info: EPM 5192 EPLD F e a tu re s • High-density, 192 macrocell, general-purpose M AX 5000 EPLD, easily integrating com plete logic boards into a single package High-speed m ulti-LAB architecture tpD as fast as 15 ns Counter frequencies up to 83.3 MHz Pipelined data rates up to 100 MHz

Contextual Info: SN54HC257, SN54HC258, SN74HC257, SN74HC258 QUADRUPLE 2ĆLINE TO 1ĆLINE DATA SELECTORS/MULTIPLEXERS WITH 3ĆSTATE OUTPUTS SCLS224B − DECEMBER 1982 − REVISED SEPTEMBER 2003 15 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D ’HC257 . . . Typical tpd = 9 ns

Contextual Info: MULTILEVEL PIPELINE REGISTERS IDT29FCT520AT/BT/CT/DT IDT29FCT521AT/BT/CT/DT Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Fastest CMOS logic family available • A, B, C and D speed grades with 5.2ns tPD • Available in DIP, SOIC, SSOP, CERPACK and LCC

Contextual Info: COM’L: -7.5 Î1 MACH210A-7 Advanced Micro Devices High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 44 Pins 32 Outputs ■ 64 Macrocells 64 Flip-flops; 2 clock choices ■ 7.5 ns 4 “PAL22V16” blocks with buried macrocells ■ tpD

Contextual Info: NC7WZ17 TinyLogic UHS Dual Buffer with Schmitt Trigger Inputs Features Description • Ultra-High Speed: tPD 3.6ns Typical into 50pF at 5V VCC •   High Output Drive: ±24mA at 3V VCC   Power Down High Impedance Inputs/Outputs   

Contextual Info: 74AUP1G57 TinyLogic Low Power Universal Configurable TwoInput Logic Gate Features Description ̇ ̇ 0.8V to 3.6V VCC Supply Operation ̇ High Speed tPD - 2.9ns: Typical at 3.3V ̇ ̇ Power-Off High-Impedance Inputs and Outputs The 74AUP1G57 is a universal configurable 2-input

Contextual Info: NC7SP126 TinyLogic ULP Buffer with Three-State Output Features Description ̇ ̇ 0.9V to 3.6V VCC Supply Operation ̇ Extremely High Speed tPD - 3.0ns: Typical for 3.0V to 3.6V VCC - 4.0ns: Typical for 2.3V to 2.7V VCC - 5.0ns: Typical for 1.65V to 1.95V VCC

Contextual Info: NC7SV05 TinyLogic ULP-A Inverter Open-Drain Output Features Description • • 0.9V to 3.6V VCC Supply Operation  Extremely High Speed tPD - 1.0ns: Typical for 2.7V to 3.6V VCC - 1.2ns: Typical for 2.3V to 2.7V VCC - 2.0ns: Typical for 1.65V to 1.95V VCC

AC245

Abstract: AC640
Contextual Info: TOSHIBA TC74AC245.640 Octal Bus Transceivers 245: 3-STATE, NON-INVERTING 640: 3-STATE, INVERTING Features: • High Speed: tpd = 3.9ns typ. at Vcc = 5V • Low Power Dissipation: lcc = 8|iA (max.) at • High Noise Immunity: Vn,h = V ml= 28% Vcc (min.) •

Contextual Info: TOSHIBA TC74AC11 Triple 3-Input AND Gate Features: • High Speed: tpd = 5.3ns typ. at Vcc = 5V • Low Power Dissipation: • High Noise Immunity: VNIH = VN,L = 28% Vcc (min.) • Symmetrical Output Impedance: ll0Hl = l0L = 24mA (min.). Capability of driving 5QQ transmission lines.

JESD22-A114

Abstract: NC7SP126 NC7SP126L6X NC7SP126P5X SC70-5 NC7SP126FHX
Contextual Info: NC7SP126 TinyLogic ULP Buffer with Three-State Output Features Description ƒ ƒ 0.9V to 3.6V VCC Supply Operation ƒ Extremely High Speed tPD - 3.0ns: Typical for 3.0V to 3.6V VCC - 4.0ns: Typical for 2.3V to 2.7V VCC - 5.0ns: Typical for 1.65V to 1.95V VCC

Contextual Info: fax id: 5000 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Featu res • B iC M O S for optimum speed/p ow er • High speed max. — 3.0 ns tpD TTL-to-ECL — 4 ns t PD ECL-to-TTL • Low skew < ± 1 ns • Can o perate on single +5V supply

Contextual Info: TOSHIBA TC74AC00 Quad 2-Input NAND Gate FEATURES: • High Speed: tpd = 3.8ns typ. at Vcc = 5V • Low Power Dissipation: Ic c = 4|jA (max.) at Ta = 25°C • High Noise Immunity: Vnih - Vml —28% Vcc (min.) • Symmetrical Output Impedance: II0hI = Iol = 24mA

JESD22-A114

Abstract: NC7SV17 NC7SV17FHX NC7SV17L6X NC7SV17P5X SC70-5
Contextual Info: NC7SV17 TinyLogic ULP-A Single Buffer with Schmitt Trigger Input Features Description ƒ ƒ 0.9V to 3.6V VCC Supply Operation ƒ Extremely High Speed tPD - 1.5ns: Typical for 2.7V to 3.6V VCC - 1.8ns: Typical for 2.3V to 2.7V VCC - 2.0ns: Typical for 1.65V to 1.95V VCC

Contextual Info: TOSHIBA TC74ACT86 Quad Exclusive OR Gate Features: • High Speed: tpd = 5.0ns typ. at Vcc = 5V • Low Power Dissipation: lcc = 4fiA (max.) at Ta = 25°C • Compatible with TTL Outputs: V, =0.8V (max.) V,„=2.0V (min.) • Symmetrical Output Impedance: ll0Hl = b i = 24mA