TO166 Search Results

STV0288

Abstract: ARGB1555 stx5105 stv0600 STi5107 st*0288 stv0288 I2C sti5107 jtag STi5107 pin out STV06000
Contextual Info: STi5107 Low-cost interactive set-top box decoder Data Brief Features – encoding of CGMS, Teletext, WSS, VPS, close caption • Enhanced ST20 32-bit VL-RISC CPU ■ Unified memory interface – up to166 MHz,16-bit wide SDR/DDR SDRAM interface ■ Programmable flash memory interface

non interruptible and burst and memory

Abstract: CY7C1395V25
Contextual Info: CY7C1395 CY7C1395V25 PRELIMINARY 2M x 36 PBSRAM with NoBL-Burst Architecture Functional Description • Pin-compatible to ZBT™ and NoBL™ devices • Supports up to166-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate

stv6110A

Abstract: sti5107 jtag STI5107 stv6000 STi5105 STV06110A st*0288 STV0288 STV0362 ST20
Contextual Info: STi5107 Low-cost interactive set-top box decoder Data Brief Features • Enhanced ST20 32-bit VL-RISC CPU ■ Unified memory interface – up to166 MHz,16-bit wide SDR SDRAM interface ■ Programmable flash memory interface ■ Programmable transport interface PTI

Contextual Info: CDCVF2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS637B – DECEMBER 1999 – REVISED JULY 2001 D D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible

Contextual Info: Freescale Semiconductor Technical Data MSC8122 Rev. 6, 5/2005 MSC8122 Quad Core 16-Bit Digital Signal Processor SC140 Extended Core SC140 Extended Core SC140 Extended Core MQBus SC140 Extended Core 128 128 SQBus Boot ROM 64 Local Bus IP Master 32 Timers Memory

PC133 registered reference design

Contextual Info: CDCVF2509A www.ti.com SCAS765A – APRIL 2004 – REVISED JULY 2004 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE FEATURES FEATURES • • • • • • • • • • • • • • • • • • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification

stx5105

Abstract: cofdm transmitter jtag st TUNER transport stream stv0288 I2C ST20 Dolby S uc IR for Tx, RX set top box dvb STB6000
Contextual Info: STM5118 Low-cost interactive FTA set-top box decoder DATA BRIEF DESCRIPTION STMicroelectronics sets a new standard for performance, price and integration in the single chip MPEG-2 set-top-box decoder market with the introduction of the STM5118. This highly integrated

CY25560

Abstract: CY25561 CY25561SC CY25561SXC CY25561SXCT
Contextual Info: CY25561 Spread Spectrum Clock Generator Features Applications • 50 to 166 MHz Operating Frequency Range ■ Desktop, notebook, and tablet PCs ■ Wide Range of Spread Selections:9 ■ VGA controllers ■ Accepts Clock and Crystal Inputs ■ LCD panels and monitors

Contextual Info: Part Number 405EZ Revision 1.22 - February 21, 2007 405EZ Preliminary Data Sheet PowerPC 405EZ Embedded Processor Features • AMCC PowerPC 405 32-bit RISC processor core operating at up to 416MHz • IEEE 1588 Precision Timing Protocol PTP controller

CDCVF2509A

Abstract: CDCVF2509APW CDCVF2509APWR PC133 registered reference design
Contextual Info: CDCVF2509A www.ti.com SCAS765A – APRIL 2004 – REVISED JULY 2004 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE FEATURES FEATURES • • • • • • • • • • • • • • • • • • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification

PC133 registered reference design

Contextual Info: CDCVF2509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS637C − DECEMBER 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D D this Device Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1

PC133 registered reference design

Contextual Info: CDCVF2510 www.ti.com SCAS638C – JULY 2001 – REVISED APRIL 2006 3.3-V PHASE-LOCK LOOP CLOCK DRIVER FEATURES • • • • • • • • • • • • • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible

Contextual Info: CY25561 Spread Spectrum Clock Generator Features By doing this, the measured EMI at the fundamental and harmonic frequencies of clock SSCLK is reduced. • 50 to 166 MHz operating frequency range ■ Wide range of spread selections: 9 This reduction in radiated energy can significantly reduce the

AN 6682

Contextual Info: ICS9248-105 Integrated Circuit Systems, Inc. Preliminary Product Preview Frequency Generator & Integrated Buffers for Celeron & PII/III Recommended Application: ALI 1641 PII/PIII chip set. Output Features: • 2- CPUs @2.5V, up to 146.22MHz • 2 - AGPCLK @ 3.3V

Contextual Info: Freescale Semiconductor Technical Data MSC8122 Rev. 10, 9/2005 MSC8122 Quad Core 16-Bit Digital Signal Processor SC140 Extended Core SC140 Extended Core SC140 Extended Core MQBus SC140 Extended Core 128 128 SQBus Boot ROM 64 Local Bus IP Master 32 Timers Memory

Contextual Info: Freescale Semiconductor Technical Data MSC8122 Rev. 8, 7/2005 MSC8122 Quad Core 16-Bit Digital Signal Processor SC140 Extended Core SC140 Extended Core SC140 Extended Core MQBus SC140 Extended Core 128 128 SQBus Boot ROM 64 Local Bus IP Master 32 Timers Memory

Contextual Info: Freescale Semiconductor Technical Data MSC8122 Rev. 9, 7/2005 MSC8122 Quad Core 16-Bit Digital Signal Processor SC140 Extended Core SC140 Extended Core SC140 Extended Core MQBus SC140 Extended Core 128 128 SQBus Boot ROM 64 Local Bus IP Master 32 Timers Memory

Contextual Info: CY25561 Spread Spectrum Clock Generator Features By doing this, the measured EMI at the fundamental and harmonic frequencies of clock SSCLK is reduced. • 50 to 166 MHz operating frequency range ■ Wide range of spread selections: 9 This reduction in radiated energy can significantly reduce the

PC133 registered reference design

Contextual Info: CDCVF2510 www.ti.com SCAS638C – JULY 2001 – REVISED APRIL 2006 3.3-V PHASE-LOCK LOOP CLOCK DRIVER FEATURES • • • • • • • • • • • • • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible

CDCVF2510

Abstract: CDCVF2510PW CDCVF2510PWR PC133 registered reference design
Contextual Info: CDCVF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS638B – DECEMBER 1999 – REVISED JULY 2001 D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible Operating Frequency 50 MHz to 175 MHz

htc hd2 pinouts

Contextual Info: Freescale Semiconductor Technical Data Advance Information MSC8122 Rev. 4, 1/2005 MSC8122 Quad Core 16-Bit Digital Signal Processor SC140 Extended Core SC140 Extended Core SC140 Extended Core MQBus SC140 Extended Core 128 SQBus 128 Boot ROM 64 Local Bus IP Master

gt64460

Abstract: powerpc 7447a EN300386 tffs marvell ethernet switch sgmii sgmii marvell GR-1089 MPC7447A marvell discovery III Tornado 2.2
Contextual Info: Katana Qp • Single or Dual PowerPC™ MPC7447A processors running at up to 1.3GHz ■ 2-Way SMP Architecture ■ ATCA PICMG 3.1 Node 1000Base-T Base Fabric + Octal High Speed GbE Fabric ■ Layer 2 or 3 Ethernet switch option ■ Quad PTMC expansion sites

Contextual Info: CDCVF2510 www.ti.com SCAS638C – JULY 2001 – REVISED APRIL 2006 3.3-V PHASE-LOCK LOOP CLOCK DRIVER FEATURES • • • • • • • • • • • • • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible

smd mark code zzz

Abstract: CY25701 CY25701FLXCT CY25701FLXIT CY3672 MARKING CODE SMD IC
Contextual Info: CY25701 Programmable High Frequency Crystal Oscillator with Spread Spectrum SSXO and No Spread Spectrum (XO) Option Features Benefits • Crystal Oscillator with Spread Spectrum Clock (SSXO) ■ Provides a wide range of spread percentages for maximum electromagnetic interference (EMI) reduction to meet