TERMINATION DIAGRAM Search Results

FAIRCHILD SMD MARKING

Contextual Info: www.fairchildsemi.com ML6553 Bus Termination Regulator Features General Description • Can source and sink up to 1A • Generates termination voltages for DDR SDRAM, SSTL_2 SDRAM, SGRAM, or equivalent memories • Generates termination voltages for active termination

F-100

Abstract: ML6553 ML6553CS-1
Contextual Info: www.fairchildsemi.com ML6553 Bus Termination Regulator Features General Description • Can source and sink up to 1A • Generates termination voltages for DDR SDRAM, SSTL_2 SDRAM, SGRAM, or equivalent memories • Generates termination voltages for active termination

Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM termination.

Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM termination.

SC2595

Abstract: SC2595EVB SC2595STRT videocard SR CAP
Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM termination.

SR CAP

Abstract: sc2595strt SC2595 SC2595EVB ST EF 017
Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM termination.

IEC-61131-2-standard

Abstract: AS-Interface circuit diagram Opto Couplers 1N4007 750W EN60947-5-2 IEC61000-4 IEC61000-4-4 IEC61000-4-6 IEC61131-2
Contextual Info: PCLT-2A Dual current limited over-voltage protected digital termination Applications • Type 1, 2 and 3 logic input termination for industrial automation ■ AS-Interface bus input termination ■ I/O termination in programmable logic controller ■ Proximity detector interface

SR CAP

Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM termination.

140 aci 030 00

Contextual Info: SC2595 Integrated Linear DDR Termination Regulator POWER MANAGEMENT Description Features The SC2595 is an integrated linear DDR termination device, which provides a complete solution for DDR termination designs; while meeting the JEDEC requirements of SSTL-2 specifications for DDR-SDRAM termination.

IEC-61131-2-standard

Abstract: STMicroelectronics DIODE marking code pclt-2at4 Marking STMicroelectronics surface zener diode AS-Interface circuit diagram
Contextual Info: PCLT-2A Dual current limited over-voltage protected digital termination Applications • Type 1, 2 and 3 logic input termination for industrial automation ■ AS-Interface bus input termination ■ I/O termination in programmable logic controller ■ Proximity detector interface

Contextual Info: LP2994 LP2994 DDR Termination Regulator Literature Number: SNVS202B LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier

transistor directory

Contextual Info: Using Calibrated On-Chip Series Termination in Stratix II Devices Application Note 384 April 2005, ver. 1.0 Introduction On-chip series termination RS OCT improves signal integrity and I/O performance due to optimized impedance matching. On-chip series termination eliminates the need for external series termination resistors

ST 9340

Contextual Info: DISCRETE SEMICONDUCTORS DATA SHEET ge M3D088 PSSI3120CA PECL termination Product specification 2001 Jul 19 Philips Semiconductors Product specification PECL termination PSSI3120CA PINNING - SOT23 FEATURES • Single channel PECL termination in a three pin SOT23

Philips MARKING CODE

Abstract: Philips Logic Marking Code marking code 10 sot23 BP317 PSSI3120CA
Contextual Info: DISCRETE SEMICONDUCTORS DATA SHEET ge M3D088 PSSI3120CA PECL termination Product specification 2001 Jul 19 Philips Semiconductors Product specification PECL termination PSSI3120CA PINNING - SOT23 FEATURES • Single channel PECL termination in a three pin SOT23

RSN 3305

Abstract: E416
Contextual Info: AND8020/D Termination of ECL Logic Devices Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE CONTENTS OF APPLICATION NOTE Introduction – DC Termination Analysis Section 3. Thevenin Equivalent/Parallel Termination

rsn 3305

Abstract: transmission lines Twisted Pair spice model MC10EP16 100EP 0.001 MF CAPACITOR AND8020
Contextual Info: AND8020/D Termination of ECL Logic Devices Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE CONTENTS OF APPLICATION NOTE Introduction – DC Termination Analysis Section 3. Thevenin Equivalent/Parallel Termination

9718h

Abstract: 11973H VC12 LEVEL ONE COMMUNICATIONS SXT6051 SXT framer HT 648 Decoder Rx 9802h
Contextual Info: DATA SHEET MAY 1998 Revision 1.1 SXT6051 STM-1/0 SDH Overhead Terminator General Description Features The SXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0

marking code R2 sot23

Abstract: PSSI3120CA
Contextual Info: DISCRETE SEMICONDUCTORS DATA SHEET age M3D088 PSSI3120CA PECL termination Product data sheet 2001 Jul 19 NXP Semiconductors Product data sheet PECL termination PSSI3120CA FEATURES PINNING - SOT23 • Single channel PECL termination in a three pin SOT23 package

CSPDDR100

Abstract: 25ph
Contextual Info: CSPDDR100 CALIFORNIA MICRO DEVICES Chip Scale DDR Termination Array Features Applications • 16 Integrated High frequency Series/Parallel Terminations • DDR Memory bus termination • SSTL Termination • Ultra small footprint Chip Scale Package • Ceramic substrate

without underfill

Abstract: CSPDDR100
Contextual Info: CSPDDR100 CALIFORNIA MICRO DEVICES Chip Scale DDR Termination Array Features Applications • 16 Integrated High frequency Series/Parallel Terminations • DDR Memory bus termination • SSTL Termination • Ultra small footprint Chip Scale Package • Ceramic substrate

1/CXD 9883

Abstract: A/CXD 9883
Contextual Info: USBUF01P6 IPAD EMI filter and line termination for USB upstream ports Features • Monolithic device with recommended line termination for USB upstream ports ■ Integrated Rt series termination and Ct bypassing capacitors. ■ Integrated ESD protection

Contextual Info: Product Overvic FEBRUARY 1998 Revision 7.0 SXT6051 STM-1/0 SDH Overhead Terminator General Description Features The SXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0

ELECTRO MAGNETIC INTERFERENCE MEASUREMENTS

Abstract: 1/CXD 9883 USBDF01W5 USBUF01P6 3M Philippines 9883
Contextual Info: USBUF01P6 IPAD EMI filter and line termination for USB upstream ports Features • Monolithic device with recommended line termination for USB upstream ports ■ Integrated Rt series termination and Ct bypassing capacitors. ■ Integrated ESD protection

Contextual Info: Obsolete Device LP2994 LP2994 DDR Termination Regulator Literature Number: SNVS202B March 28, 2011 LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier