TCWP Search Results

Contextual Info: irrte1* M51C256H HIGH PERFORMANCE RIPPLEMODETm 256K x 1 CHMOS DYNAMIC RAM M ilita ry M51C256H-15 M51C256H-20 Maximum Access Time ns 150 200 Maximum Column Address Access Time (ns) 70 90 High Reliability Ceramic— 16 Pin DIP Ripplem ode Operation — Continuous Data Rate over 12 MHz

FC24P

Abstract: TC64
Contextual Info: T C 2A3 S 5 J o •¡ M k a -e í í í í «*, ■ A F flE # * # !« * t . ffltX E S fft* # { 1 K M M E L U ■æ * s ï * f i Æ # , îfcs ¿ a E Æ m eft K »aW K S K «3S æ «», H Æ Ïtt lif t * ± . f ia i t r ä g t £ ^ TCÎiltTCMfc.- I ! Ti'MI1rc sa ft-

Contextual Info: FUJITSU IM MB85237-10 9 S CR AM MODULE X MB85237-12 TS029-A881 Jan. 1988 1,048,576 x 9 BIT DYNAMIC RANDOM ACCESS MEMORY MODULE The F u j i t s u MB85237 is a fully decoded, dynamic CMOS random access memory module with nine MB81C1002, in 26-pin SOJ p a c k a g e s , and nine .22yF decoupling capa­

Contextual Info: 4,194,304 WORD X 1 BIT'DYNAMIC RAM * This is advanced information and specifications are subject to change without notice. DESCRIPTION The TC514100JL/ZL is the new generation dynamic RAM organized 4,194,304 words by 1 bit. The TC514100JL/ZL utilizes TOSHIBA'S CMOS Silicon gate process technology as well as

TC51440ASJ

Contextual Info: TOSHIBA TC514410ASJ-60/70/80 1,048,576 WORD X 4 BIT DYNAMIC RAM DESCRIPTION The TC514410ASJ is the new generation dynamic RAM organized 1,048,576 word by 4 bit. The TC514410ASJ utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit techniques

R5F61668RFPV

Abstract: R5F61664RFPV R5F61668RN50FPV R5F61663RFPV A18E A1719 transistor NEC D 587 lsi tms 1951 nl 1117 3.3 DKC mark
Contextual Info: REJ09B0412-0200 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 H8SX/1668R Group, H8SX/1668M Group

LGA144

Abstract: XORB LGA-144 4435* mos A18E SR 2370R ic 555 block diagram 1041 p26 HD64F2378RVFQ marking 1052
Contextual Info: REJ09B0109-0600 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2378, H8S/2378R Group Hardware Manual

Contextual Info: HS-3273 ¡lì HARRIS CMOS Bus Interface Unit Mil-Std-1553 Protocol Bus Interface Circuit Features Pinout DIP • M il-Std-1553 Com patible • Up To 5M H z Data Rate For N on-M il-S td-1553 Applications • Parallel to Serial Transm itter Data Conversion TO P VIEW

Contextual Info: HM51W16160A Series HM51W18160A Series 1048576-word x 16-bit Dynamic Random Access Memory HITACHI ADE-203-217B Z Rev. 2.0 Jul. 2, 1996 Description The Hitachi HM51W16160A Series, HM51W18160A Series are CMOS dynamic RAMs organized as 1,048,576-word x 16-bit. They employ the most advanced CMOS technology for high performance

Contextual Info: intei M2118 FAMILY 16,384 x 1 BIT DYNAMIC RAM M IL IT A R Y M2118-4 120 270 320 Maximum Access Time ns Read, Write Cycle (ns) Read-Modify Cycle (ns) • Single +5V Supply, ±10% Tolerance M2118-7 150 320 410 ■ RAS Only Refresh ■ HMOS Technology ■ Low Power: 150 mW Max. Operating

WO1M

Abstract: Nippon capacitors
Contextual Info: HB56H164EJ Series 1,048,576-word x 64-bit High Density Dynamic RAM Module HITACHI ADE-203-697A Z Rev. 1.0 Dec. 27, 1996 Description The HB56H164EJ belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The

Contextual Info: TSS901E Intelligent and Flexible IEEE 1355 Communication Controller for Space Description and Applications The TSS901E provides an interface between a DataStrobe link - according to the IEEE Std 1355-1995 specification carrying a simple interprocessor communication protocol - and a data processing node

SMCS332

Abstract: ERC32 MG1140E TSC21020F TSC695E TSS901E
Contextual Info: Features • 3 identical bidirectional link channels allowing full duplex communication under selectable transmit rate from 1.25 up to 200 Mbit/s in each direction • A COmmunication Memory Interface COMI provides autonomous accesses to a • • • •

SMCS332

Abstract: 5962-01A1701QXC ERC32 C104 MG1140E TSC21020F TSC695E TSS901E W359
Contextual Info: Features • 3 identical bidirectional link channels allowing full duplex communication under selectable transmit rate from 1.25 up to 200 Mbit/s in each direction • A COmmunication Memory Interface COMI provides autonomous accesses to a • • • •

R5F61664

Abstract: 4435* mos Nippon capacitors
Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

ERC32

Abstract: MG1140E SMCS332 TSC21020F TSC695E TSS901E memory arbitration scheme
Contextual Info: Features • 3 identical bidirectional link channels allowing full duplex communication under selectable transmit rate from 1.25 up to 200 Mbit/s in each direction • A COmmunication Memory Interface COMI provides autonomous accesses to a • • • •

MQ4A

Abstract: um227 NLMQ4
Contextual Info: KM44C268C CMOS DRAM 2 5 6 K X 4 Bit CMOS Dynamic RAM with Static Column Mode Write Per Bit Mode FEATURES GENERAL DESCRIPTION • Performance range: The Samsung KM44C268C is a high speed CMOS 2 6 2 ,1 4 4 X 4 Dynamic Random Access Memory. Its design is optimized for high performance applications

Contextual Info: M O S EL V IT E L IC V53C8129H ULTRA-HIGH PERFORMANCE, 128K X 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 35 40 45 50 Max. RAS Access Time, tRAC 35 ns 40 ns 45 ns 50 ns Max. Column Address Access Time, (Icu ò 18 ns 20 ns 22 ns 24 ns Min. Fast Page Mode With EDO Cycle Time, (tpC)

Contextual Info: GM71C S 18160C(CL) 1Mx16,SV, 1K Ref, FP Description The F e a tu re s G M 7 1 C ( S ) 1 81 6 0 C / C L generation dynamic x 16 bit. RAM is th e n e w organized 1,048,576 G M 7 1 C (S )1 8 1 6 0 C / C L has realized higher density, higher performance and various

HYM532814

Abstract: TRA8 L HYM536410 HYM532100AM HYM532100
Contextual Info: TIMING DIAGRAM INDEX E D O 4-Byte SIMM HYM532124AW HYM532224AW . . . . . . 1Mx32 EDO 2Mx32 EDO 2Mx32 EDO 1Mx 16 based . . . . . 1Mx 16 based . . . . . 2Mx8 based . . . . . EDO TIMING DIAGRAM -1 EDO TIMING DIAGRAM -1 . .

irf 539

Abstract: marking code H02 HFC8 Nippon capacitors
Contextual Info: REJ09B0579-0100 16 H8S/2426Z Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series H8S/2426Z R4F2426Z All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by

Contextual Info: O K I Semiconductor E2G0033-17-41 4,194,304-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM5116400B is a 4,194,304-word x 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM5116400B achieves high integration, high-speed operation, and low-power

Contextual Info: O K I Semiconductor MSM5 18200 _ E 2 G 00 28 - 17-41 4,194,304-Word x 2-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM518200 is a 4,194304-word x 2-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM518200 achieves high integration, high-speed operation, and low-power

d42s65405g5

Abstract: NEC D42S65405 D42S65405G5-A50-7J D42S65405 42S65405 42S844Q5G5-A60 IC MARKING A60 MPD42S64405
Contextual Info: DATA SHEET NEC / MOS INTEGRATED CIRCUII _ //¿PD42S64405,4264405,42S65405,4265405 64M-BIT DYNAMIC RAM 16 M-WORD BY 4-BIT, EDO Description The /¿PD42S64405, 4264405, 42S65405, 4265405 are 16,777,216 words by 4 bits CMOS dynamic RAMs with optional EDO. EDO >s a kind of the page mode and is useful for the read operation.