T902 Search Results

Contextual Info: @ T90220 M ITEL Octal IMA/UNI PHY Device Advance Inform ation S E M IC O N D U C T O R DS5036_ISSUE 2_ November 1998 Features Ordering Information C ost effective, single chip, 8 -po rt ATM IMA and UNI processor M T90220AL

Contextual Info: $ T90220 M ITEL Octal IMA/UNI PHY Device Advance Inform ation S E M IC O N D U C T O R DS5036_ISSUE 1_ November 1998 Features Ordering Inform ation Cost effective, single chip, 8-p o rt ATM IMA and UNI processor M T90220AL

ATIC 112

Abstract: T902
Contextual Info: T902 Ethernet Twisted-Pair Media Attachment Unit The L X T902 tw isted-pair M edia A ttachm ent Unit TPM A U is designed to allow E thernet connections to use the existing tw isted-pair w iring plant through an Ethernet A ttachm ent U nit Interface (AUI). T he LX T902 provides

T902 transformer

Abstract: TRANSFORMER T902
Contextual Info: DATA SHEET "• V y • - 7 - : > w - . •. - r4 . \ a p r il , 1996 T902 Ethernet Twisted-Pair Media Attachment Unit T he LX T902 tw isted-pair M edia A ttachm ent U n it TPM A U is designed to allow E thernet connections to use the existing tw isted-pair w iring plant through an E thernet A t­

N010-0554-T902

Abstract: T902
Contextual Info: RoHS compliant Part Number: N010-0554-T902

tms4256

Abstract: TMS4266
Contextual Info: INSTR TM4256EL9, TM4256GU9 262,144 BY 9-BIT DYNAMIC BAM MODULES 7“-ifc-23-/7 25E D SEPTEMBER 1986 — REVISED M ARCH 1968 A SIC /MEMORY 262,144 x 9 Organization TM4266EL9 . . . L SMQLE-IN-UNE PACKAGE (TOP VIEWl_ Slngla 5-V Supply (10% Tolerance)

AX2022

Abstract: TACT2150 D6142
Contextual Info: TACT2150 512 X 8 CACHE ADDRESS COMPARATOR D 2 9 9 3 . JA N U A R Y 1 9 8 7 - R E V IS E D SEPTEM BER 1967 Address to MATCH Valid Time TACT2150-20 . . . 20 ns max TACT2150-30 . . . 30 ns max DW, JD . OR NT PACKAGE 300-Mil 24-Pin Ceramic Side-Brazed or Plastic Dual-In-Line or Small Outline

ltl17

Contextual Info: flTblTSS 0 0 7 7 0 0 2 0 TM4256FC1 1,048,576 BY 1B IT DYNAMIC RAM MODULE INS TR A SIC /MEMORY OCTOBER'19 9 5 —REVISED FEBRUARY 1988 BSE D 1 ,0 4 8 ,5 7 6 x 1 Organization TM 4266FC 1 . . C SINGLE-IN-LINE PACKAGE (TOP VIEW) Single 5-V Supply (10 % Tolerance)

aoo8

Abstract: smd ic lv 1116 ao65 Tolerance limit for basic dimensions in ansi y14
Contextual Info: < Military 10H518 M O T O R O LA Dual 2-Wide 3-Input “OR-AND” Gate ELECTRICALLY TESTED PER: 5962-8755901 The 10H518 is a basic logic building block providing the OR/AND function, use­ ful in data control and digital multiplexing applications. This M ECL 10H part is a functional/pinout duplication of the standard M ECL

TL 2272 M

Contextual Info: <g> M O T O R O L A Military 10507 Triple 2 Input Exclu sive “O R ’VExclusive “NOR” Gate ELEC TRICA LLY T E STE D PER: MIL-M-38510/06005 M The 10507 is a triple 2 input exclusive OR/NOR gate. P ll/ l/ ll • 40 m W Max/Gate No Load • tpcj = 2.8 ns typ

LC6502

Abstract: LC7060 ic la 7522 sanyo lc7560 Sanyu thd2 buzzer
Contextual Info: 0 SEMICONDUCTOR CORP 3SE D m 7 cic1707t, G O O Ö O b S wr 5 B T '7H-0& O l w 3012A ' CMOS LSI Electronic Volume Control for Graphic Equalizer $1890C The 3-chip configuration consisting of the LC7520, a controller LC7060 or general-purpose microcomputer LC6502, etc. , and a display LSI (LC7560—»LCD,

T74LSxx

Contextual Info: SS T54LS395/ 395A Ü 4tS39S/395A 4-BIT SHIFT REGISTER WITH 3-STATE OUTPUTS DESCRIPTION The T54LS395/395A/T74LS395/395A are 4-Bit Re­ gisters with 3-state outputs and can operate in ei­ ther a synchronous parallel load or a serial shift-right mode, as determined by the Select in­

T74LS273B1

Abstract: LS273 T54LS273D2 T74LS273C1 LHAD
Contextual Info: T54LS273 T74LS273 S S 8-BIT REGISTER WITH CLEAR DESCRIPTION The T54LS273/T74LS273 is a high speed 8-Bit Re­ gister. The register consists of eight D-Type Flipflops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing.

pc014

Abstract: LS258
Contextual Info: a s QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS DESCRIPTION The LSTTL/MSI T54LS258/258A, T74LS258/258A s a Quad 2-Input Multiplexer with 3-state outputs. Four bits of data from two sources can be selec­ ted using a Common Data Select input. The four outputs present the selected data in the comple­

Am2963

Contextual Info: Am29833A/Am29853A/Am29855A Parity Bus Transceivers VSS86ZUJV/V8S86ZUIV/VSC86ZUIV DISTINCTIVE CHARACTERISTICS • High-speed bidirectional bus transceivers for processor organized devices - T-R delay = 6 ns typical - Rj-Parity delay = 9 ns typical • Error flag with open-collector output

Contextual Info: Am29C827/Am29C828 Am29C927/Am29C928 Am29C827/Am29C828 Am29C927/Am29C928 High-Performance CMOS Bus Buffers DISTINCTIVE CHARACTERISTICS • • • High-speed CMOS buffers and inverters - D-Y delay = 7 ns typical Low standby power JEDEC FCT-compatible specs

Am29C82

Contextual Info: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance CMOS Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs •

29c833

Abstract: 29C933 amd 955
Contextual Info: Am29C833/Am29C853/Am29C855 Am29C933/Am29C953/Am29C955 Am29C833/Am29C853/Am29C855 Am29C933/Am29C953/Am29C955 High-Performance CMOS Parity Bus Transceivers DISTINCTIVE CHARACTERISTICS • • • • High-speed CMOS bidirectional bustransceivers - T-R delay = 6 ns typical

Contextual Info: TEXAS INSTR -CASIC/MEMORY} Ì7 Ô Ë | flìtlTES D074Ô31 □ 262,144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY FEBRUARY 1988 262,144 x 4 Organization JD PACKAGE TOP VIEW Performance Ranges: AC C ESS AC C ESS AC C ESS TIM E TIM E TIM E • e 4 5 ns *a(CA)

TSP50C50

Abstract: TSP50C4X TSP60C19 paralell input serial output shift register
Contextual Info: TSP60C19 SPEECH DATA ROM 4.0 TSP60C19 GENERAL DESCRIPTION THE TSP60C19 IS A 256K BIT ROM FABRICATED IN CMOS TECHNOLOGY FOR LOW OPERATING AND STANDBY POWER CONSUMPTION. THE DESIGN IS OPTIMIZED FOR THE DATA STORAGE REQUIREMENTS OF SYNTHETIC SPEECH SYSTEMS BUT MAY

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM HD74HCT137 TB DE 4 4 ^ 2 0 3 # 3-to-8-line Decoder/Dem ultiplexer with Address Latch | PIN ARRANGEMENT r-J-a T - , T ¡ ] Vcc B[T - B c^ - C Yi u jy. GL Yi ÏÏ]V i G L^ - A Yfl - C¡ Yi ¡ 2] Yi G i^ - Gi

Contextual Info: H I T A C H I / L O G I C / A R R A Y S / M E M H D 74H C 374 H D 74H C 534 I S D Ë J M a t a d a 1 5 1 3 fi • Octal D-type Flip-Flops with 3 -state outputs • Octal D-type Flip-Flops (with inverted 3 -state o u tp u ts ) 92D These devices are positive edge triggered flip-flo ps. The d if­

Contextual Info: H D 74A C 165/H D 74A C T 165 # P a r a lle llo a d 8-bit Shift Register Description Pin Assignment This 8-bit serial shift register shifts data from Qa to Q h when clocked, Parallel inputs to each stage are enabled by a low level at the Shift/Load Input.

Contextual Info: "HITACHI/ L O G I C / A R RA YS /M En TS D E I 4 4 ^ 5 0 3 DD Id 3 Mb 4 | .9 2 D HD74HC76 • 10346 D T ~ Ÿ é ~ â 7 -û 7 Dual J-K Flip-Flops with Preset and Clear • PIN ARRANGEMENT Each flip -flo p has independent J, K , preset, clear, and clock