T54LSX Search Results

IR2E16

Abstract: LS125 16CIF truth table NOT gate 74 ls126 HC 125A
Contextual Info: LS125/125A - QUAD 3-STATE BUFFER LOW ENABLE LS126/126A - QUAD 3-STATE BUFFER (HIGH ENABLE) DESCRIPTION The T54LS/T74LS125/125A/126/126A are high speed QUAD 3-STATE BUFFERS WITH ACTIVE HIGH ENABLES fabricated in LOW POWER SCHOTTKY tecnology. B1 Plastic Package

pc014

Abstract: LS258
Contextual Info: a s QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS DESCRIPTION The LSTTL/MSI T54LS258/258A, T74LS258/258A s a Quad 2-Input Multiplexer with 3-state outputs. Four bits of data from two sources can be selec­ ted using a Common Data Select input. The four outputs present the selected data in the comple­

TDA0161 equivalent

Abstract: 1N3393 BDX54F equivalent byt301000 bux transient voltage suppressor ST90R9 ua776mh sgs 2n3055 Transistor morocco mje13007 inmos transputer reference manual
Contextual Info: SHORTFORM 1995 NOVEMBER 1994 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:

T74LS

Abstract: LS645 LS640 LS641
Contextual Info: s G S-THOMSOn D7E D I Lüw P U W tK S U H U INTEGRATED CIRCUITS . _ 67C . 7^5^53? 001L3T? I ;T54LS640/641/645j I IKY D 16526 fl 7c- 5 ' 2 " 3 i PRELIMINARY DATA O CTAL BUS TRANSCEIVERS DESCRIPTION The T54LS/T74LS640/641/645 are octal bus tran­

LS147

Abstract: T74LSXXX PIN 74LS147
Contextual Info: SGS M i PRELIMINARY DATA IO-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS 16 DESCRIPTION 16 T \ [ 1 i 1 These priority Encoders decode the inputs to en­ sure that only the highest order data line is enco­ ded. All inputs and outputs data of both devices

T74LS155

Contextual Info: S G S-THONS ON D7E D I 7 ^ 2 3 7 DDlblOQ 3 I LOW POWER SCHOTTKY INTEGRATED CIRCUITS 6 T C - 1 6 2 2 9 . T -6 6 -2 1 -5 5 DUAL 1-OF-4 DECODER/DEMULTIPLEXER DESC RIPTIO N The TTL/MSI T54LS155/T74LS155 and T54LS156/ T74LS156 are high speed Dual 1-of-4 Decoder/De­

LS147

Abstract: El 3021
Contextual Info: s G S-THOMSON 07E D | 7e]a 1-237 DDlbD?^ S | LOW POWER SCHOTTKY INTEGRATED CIRCUITS i^ l4 L S 1 4 7 /t4 8 T74LS147/148 T-66-21-57 67C 16 208 PRELIMINARY DATA 10-LINË-TO-4-L1NE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS DESCRIPTIO N These priority Encoders decode the inputs to en­

TOP 244 gn

Abstract: T74LS240 S16C
Contextual Info: S G S-THOfISON D7E D | 7 ^ 2 3 ? DDlbÈGS b | ."'.1 LOW POWER SCHOTTKY INTEGRATED & riY T 5 4 L $ 2 4 0 /2 4 1 /2 4 4 ; p n V;T74LS240/241/244| U l K O t. U I I O _ 67C 1 6 3 3 4 , . D I . , . T - 52.-&7_ OCTAL BUFFER/LINE DRIVERS W ITH 3-STA TE OUTPUTS

Q01t

Contextual Info: S G S-THOnSON D7E D | 7 ^ 2 3 7 if* 00lb3bû 1 | 1 LOW POWER SCHOTTKY I a INTEGRATED CIRCUITS 67C 15497 D T-66-21-51 QUAD 2-PORT REGISTER DESCRIPTION The T54LS/T74LS398/399 are Quad 2-Port Regi­ sters. They are the logical equivalent of a quad 2-input multiplexer followed by a 4-bit edgetriggered register. Selection between two 4-bit in­

LS155

Abstract: demultiplexer truth table LS156 T74LS156 74 ls 155 demultiplexer
Contextual Info: in i ss DUAL 1-0F-4 DECODER/DEMULTIPLEXER DESCRIPTION The TTL/MSI T54LS155/T74LS155 and T54LS156/ T74LS156 are high speed Dual 1-of-4 Decoder/De­ multiplexers. These devices have two decoders with common 2-bit Address inputs and separate ga­ ted Enable inputs. Decoder “ a” has an Enable gate

47ls148

Abstract: LS147 LS148 74LS147
Contextual Info: » PRELIMINARY DATA 10-LINE-T0-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS 16 T Y V 1 16 n /y \ I DESCRIPTION 1 These priority Encoders decode the inputs to en­ sure that only the highest order data line is enco­ ded. All inputs and outputs data of both devices

ls293

Abstract: ls290 binary to BCD 8421 LS293-4-BIT LS90 LS93 3 bit ripple counter T74LS293
Contextual Info: ses LS290-DECADE COUNTER LS293-4-BIT BINARY COUNTER DESCRIPTION T 5 4 L S /T 7 4 L S 2 9 0 and T 5 4 L S /T 7 4 L S 2 9 3 are - gn-speed 4-bit ripple type counters partitioned in•: rwo sections. E ach counter has a divide-by-two section and either a divide-by-five L S 2 90 or

connecting diagram for ic 74 08

Abstract: H2635
Contextual Info: DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS109-109A consist of two high sjjeed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operatioji as a D flip-flop by simply

LS365A

Abstract: rl66 C6017 LS366 LS366A LS367A
Contextual Info: 3-STATE HEX BUFFERS DESCRIPTION These devices are high-speed Hex Buffers with 3-state outputs. They are organized as single 6-bit or 2-bit/4-bit, with inverting or non-inverting data D paths. The outputs are designed to drive 15 TTL Unit Loads or_60 Low Power Schottky loads when

Contextual Info: ss DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP $0^ DESCRIPTION The T54LS/T74LS113/113A offers individual J, K, set and clock inputs. These monolithic dual flipflops are designed so that when the clock goes HIGH, the inputs are enabled and data will be ac­ cepted. The logic level of the J and K may be allo­

Contextual Info: W M s LS190 - PRESETTABLE BCD/DECADE UP/DOWN COUNTERS LS191 - PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS 1 1 DESCRIPTION The T 54L S 190/T74LS 190 is a synchronous UP/DO W N BCD Decade 8421 Counter and the T54LS191/T74LS191 is a synchronous UP/DOW N Modulo-16 Binary Counter. State changes of the

Contextual Info: s G S-THONSON 07E D | 7 ^ 2 3 7 D01b24S LOW POWER SCHOTTKY INTEGRATED CIRCUITS - 67 C 16374 D T-66-21-51 QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS DESCRIPTION ; The LSTTL/M SIT54LS258/258A , T74LS258/258A Is a Quad 2-Input Multiplexer with 3-state outputs.

JT54LS

Contextual Info: S G S-THOrïSON D7E D g 7 1 2 T 2 3 7 LOW POWER SCHOTTKY INTEGRATED CIRCUITS _ 67C 1 55 12 T-5 Z-07 OCTAL BUFFER/LINË DRIVERS WITH 3-STATE OUTPUTS DESCRIPTIO N The T54LS/T74LS540/541 are Octal Buffers and Line Drivers. Although they have the same func­

LS126

Abstract: ls125
Contextual Info: a s LS125/125A - QUAD 3-STATE BUFFER LOW ENABLE LS126/126A - QUAD 3-STATE BUFFER (HIGH ENABLE) DESCRIPTION B1 Plastic Package The T54LS/T74LS125/125A/126/126A are high speed QUAD 3-STATE BUFFERS WITH ACTIVE HIGH ENABLES fabricated in LOW POWER SCHOTTKY tecnology.

L5357

Contextual Info: S G S-THOMSON 07E D I 7 ^ 2 3 7 T54LS257/257A 1 T74LS257/257A OOlbEBö □ I LOW POWER SCHOTTKY 67C L5357 INTEGRATED CIRCUITS T-66-21-51 QUAD 2-IN P U T MULTIPLEXER W ITH 3-STA TE OUTPUTS DESCRIPTIO N The LSTTL/MSI T54LS257/257A, T74LS257/257A is a Quad 2-Input Multiplexer with 3-state outputs.

t114a

Abstract: 1t4a T54LS/T74LS114/114A
Contextual Info: S G K ? C m Î i S-THOnSON $ 1 ÎM 07E M D | 7^5^53? 0 UJi hü 31 4 | LOW POWER SCHOTTKY INTEGRATED CIRCUITS i l Ì T 7 4 L S t1 4 |M 67C 1 6 1 6 7 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T54LS/T74LS114/114A offer common clock and common clear inputs and individual J, K, and

LS540

Contextual Info: PRELIMINARY DATA OCTAL BUFFER/LINE DRIVERS WITH 3-STATE OUTPUTS DESCRIPTION The T54LS/T74LS540/541 are Octal Buffers and Line Drivers. Although they have the same func­ tions as LS240 and LS241, they offer a pinout with inputs and outputs on apposite sides of the pac­

Contextual Info: 4-STAGE PRESETTABLE RIPPLE COUNTERS DESCRIPTION The T54LS196/T74LS196 decade counter is par­ titioned into divide-by-two and divide-by-five sec­ tion which can be combined to count either in BCD 8 ,4,2 , 1 sequence or in a bi-quinary mode produ­ cing a 50% duty cycle output. The T54LS197/

LS93

Abstract: LS90 T74LS90 LS92 T74LSXX bcd counter 7490 bcd counter 74 90
Contextual Info: $90/ 92/93 890/92/93 LS90 DECADE COUNTER LS92 DIVIDE-BY-TWELVE COUNTER LS93 4-BIT BINARY COUNTER DESCRIPTION 1 T h e T 5 4 L S 9 0 /T 7 4 L S 9 0 , T 5 4 L S 9 2 /T 7 4 L S 9 2 and T 5 4 L S 9 3 /T 7 4 L S 9 3 are high-speed 4-bit ripple ty­ pe counters partitioned into two sections. Each