T22B Search Results

Asus MONITOR MOTHERBOARD CIRCUIT MANUAL

Abstract: T2D 83 diode gp026 st GP025 82430TX 82371EB Asus PC MOTHERBOARD CIRCUIT schematic diode T75A Asus PC MOTHERBOARD CIRCUIT MANUAL 8272A floppy disk controller block diagram
Contextual Info: PRELIMINARY DRAFT Intel Extended Temperature 82371EB PCI-TO-ISA/IDE Xcelerator PIIX4E Datasheet  Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers  Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation Supported Kits for both Pentium and

DDC112

Abstract: DDC112U DDC112UK rms225
Contextual Info: DDC112 DDC 112 DD C11 2 ® SBAS085A – JANUARY 2000 – REVISED – AUGUST 2002 Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● MONOLITHIC CHARGE MEASUREMENT ADC ● DIGITAL FILTER NOISE REDUCTION: 3.2ppm, rms ● INTEGRAL LINEARITY:

Contextual Info: A B W A N O B O N IP O R Q W O Q N in te i 82091AA ADVANCED INTEGRATED PERIPHERAL AIP • Single-Chip PC Compatible I/O Solution for Notebook and Desktop Platforms: — 82078 Floppy Disk Controller Core — Two 16550 Compatible UARTs — One Multi-Function Parallel Port

82430LX

Contextual Info: in te * 82433LX/82433NX LOCAL BUS ACCELERATOR LBX Supports th e Full 64-bit Pentium- Processor Data Bus at Frequencies up to 66 MHz (82433LX and 82433NX) Dual-Port Architecture Allows Concurrent Operations on the Host and PCI Buses Drives 3.3V Signal Levels on the CPU

Contextual Info: intJ. 82375EB PCI-EISA Bridge PCEB Provides the Bridge Between the PCI Bus and EISA Bus 32-Bit Data Paths 100% PCI and EISA Compatible — PCI and EISA Master/Slave Interface — Directly Drives 10 PCI Loads and 8 EISA Slots — Supports PCI at 25 MHz to 33 MHz

82378ib

Contextual Info: A P M Ä M ! DM iP© I^[ìfflA'irD@ N] in te i 82378IB SYSTEM I/O SIO Provides the Bridge Between the PCI Bus and ISA Bus Arbitration for PCI Devices — Four PCI Masters are Supported — Fixed, Rotating, or a Combination of the Two 100% PCI and ISA Compatible

T32A scr

Abstract: t17c floppy controller pinout Intel 82072 intel floppy disk controller 8272 82091AA T16E 82077AA 82077SL SA10
Contextual Info: 82091AA ADVANCED INTEGRATED PERIPHERAL AIP Y Single-Chip PC Compatible I O Solution for Notebook and Desktop Platforms 82078 Floppy Disk Controller Core Two 16550 Compatible UARTs One Multi-Function Parallel Port IDE Interface Integrated Back Power Protection

Cyrix M2 CPU

Abstract: cyrix 8086 opcode of mov ax,bx MSR10 296-pin Cyrix 6x86mx 300GP CYRIX CORPORATION
Contextual Info: &\UL[ 0,Œ '$7$%22. Š April 1998 Updates for this manual can be obtained from Cyrix Web site: www.cyrix.com. 1998 Copyright Cyrix Corporation. All rights reserved. Printed in the United States of America Trademark Acknowledgments: Cyrix is a registered trademark of Cyrix Corporation.

T3D 34 diode

Abstract: 82440LX Diode T3D 57 t57b T27b t59b T31C Transistor t59c ISA BUS spec t119
Contextual Info: E DATASHEET ADDENDUM 82371AB PIIX4 PCI ISA IDE Xcelerator Timing Specifications September 1997 Order Number: 290548-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions

Contextual Info: 6 x 8 6 M X PROCESSOR Enhanced Sixth-Generation CPU Compatible with MMX Technology 4 .0 ELECTRICAL SPECIFICATIONS 4.1 Electrical Connections connected to VCC2 2.9 volts , 28 pins connected to VCC3 (3.3 volts), and 53 pins connected to Vss (ground). 4 .1 .2

Contextual Info: Elan SC400 and ElanSC410 AMDÎ1 Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers DISTINCTIVE CHARACTERISTICS Elan™SC400 and ElanSC410 Microcontrollers • ■ ■ Standard PC/AT system logic PICs, DMACs, timer, RTC - DOS, ROM-DOS, Windows, and industrystandard BIOS support

82335

Abstract: intel 82230
Contextual Info: in te i 82335 SX HIGH-INTEGRATION INTERFACE DEVICE FOR 386 SX MICROPROCESSOR BASED PC-AT SYSTEMS • Operates with the 8 2 2 3 0 and 8 2 2 3 1 to Provide 1 0 0 % IBM ATtm Compatibility ■ ■ Optimized for 16 MHz and 2 0 MHz SX Microprocessor Based PC-AT

Contextual Info: DDC DD C11 2 112 DDC112 ® SBAS085B – JANUARY 2000 – REVISED OCTOBER 2004 Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● MONOLITHIC CHARGE MEASUREMENT A/D CONVERTER ● DIGITAL FILTER NOISE REDUCTION: 3.2ppm, rms ● INTEGRAL LINEARITY:

Contextual Info: Preliminary Data Sheet July 1995 m A T& T Microelectronics DSP1605 Digital Signal Processor 1 Features 2 Description • For 5 V operation: — 25 ns instruction cycle time 40 MIPS — 30 ns instruction cycle time (33 MIPS) ■ For 3.3 V operation: — 31.25 ns instruction cycle time (32 MIPS)

386SX

Abstract: 82385SX t23b 82358 82385 t44a 387SX SA9C a82385 intel 386 SX LP
Contextual Info: in te i 82385SX HIGH PERFORMANCE CACHE CONTROLLER Im proves 386 SX System Perform ance — Reduces A verage CPU W ait States to Nearly Zero — Zero W ait State Read Hit — Zero W ait State Posted Mem ory W rites — Allows O ther Masters to Access the

WE-DSP32C

Abstract: we dsp32 7495 4-bit shift register dsp32c WEDSP32 dsp32 att OXE800 AT&T dsp32 PDB11 sy 164
Contextual Info: NOV i l 19M . Data Sheet ^ AT&T r Microelectronics WIE DSP32C Digital Signal Processor Introduction Description AT&T is the industry leader in floating-point digital signal processing. AT&T's DSP32 architecture was introduced in 1985 and is now the accepted

Contextual Info: DDC DD C11 2 112 DDC112 ® SBAS085B – JANUARY 2000 – REVISED OCTOBER 2004 Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● MONOLITHIC CHARGE MEASUREMENT A/D CONVERTER ● DIGITAL FILTER NOISE REDUCTION: 3.2ppm, rms ● INTEGRAL LINEARITY:

CHN T4 1060

Abstract: prma 1824 MN103S AM32 MN103S00 MN103S33N AN-1998 932DM t509 r5 cpu am32
Contextual Info: MICROCOMPUTER MN103S00 MN103S33N/F33N LSI 説明書 Pub.No.23233-011 PanaXSeriesは松下電器産業株式会社の商標です。 その他記載された会社名及びロゴ、製品名などは該当する各社の商標または登録商標です。

Contextual Info: DDC DD C11 2 112 DDC112 ® SBAS085B – JANUARY 2000 – REVISED OCTOBER 2004 Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● MONOLITHIC CHARGE MEASUREMENT A/D CONVERTER ● DIGITAL FILTER NOISE REDUCTION: 3.2ppm, rms ● INTEGRAL LINEARITY:

Contextual Info: DDC DD C11 2 112 DDC112 ® SBAS085B – JANUARY 2000 – REVISED OCTOBER 2004 Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● MONOLITHIC CHARGE MEASUREMENT A/D CONVERTER ● DIGITAL FILTER NOISE REDUCTION: 3.2ppm, rms ● INTEGRAL LINEARITY:

440BX

Abstract: Diode T3D 57 t26b t2d t3d T3D 53 diode T3D 62 82443BX t2d 68 T13A T14A
Contextual Info: 82443BX Host Bridge/Controller Electrical and Thermal Specification Timing Specification Datasheet Addendum Product Features • ■ ■ Processor/host bus support —Optimized for Pentium II processor at 100 MHz system bus frequency; Support for 66 MHz

T55B

Abstract: T71A t19c t17c t61b t58b t57b T27b t65a T3D 62
Contextual Info: 82371AB PCI ISA IDE Xcelerator PIIX4 23.0 Clock, Reset, ISA Bus, X-Bus, and Host Timing Diagrams Figure 41. Clock Timing Period High Time PCICLK, SYSCLK, OSC 2.0V 0.8V Low Time Fall Time Rise Time Figure 42. Reset Inactive Timing SUS_STAT[1:2]# t2f PCIRST#, RSTDRV

2BSM

Abstract: 8BSM
Contextual Info: 2 . 54±°-3 C±0.3 D±0.3 ED— EEtl LO 00 CD LO CO CD O □ O □ • D i m e n s i o n s A A and B 2 . 54 5.08 7 . 62 10.16 12.7 15.24 17.78 20.32 22.86 25 . 4 27.94 30.48 33.02 35 . 56 38 . 1 40.64 43.18 OJ LO No. of contacts n — 4 6 8 10 12 14 16

t43b

Abstract: T78A t78b T49B T61-T62 T71-T72
Contextual Info: 82357 11.0 A.C. SPECIFICATIONS The A.C. specifications given in the following tables consist of output delays and input setup and hold requirements. The A.C. diagram’s purpose is to illus­ trate the clock edges and specific signal edges from which the timing parameters are measured. The