T27B Search Results

Asus MONITOR MOTHERBOARD CIRCUIT MANUAL

Abstract: T2D 83 diode gp026 st GP025 82430TX 82371EB Asus PC MOTHERBOARD CIRCUIT schematic diode T75A Asus PC MOTHERBOARD CIRCUIT MANUAL 8272A floppy disk controller block diagram
Contextual Info: PRELIMINARY DRAFT Intel Extended Temperature 82371EB PCI-TO-ISA/IDE Xcelerator PIIX4E Datasheet  Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers  Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation Supported Kits for both Pentium and

82706

Contextual Info: P W B U M M M in te T 82706 INTEL VIDEO GRAPHICS ARRAY • Single Chip Video Graphics Array for IBM PC/XT/AT*, Personal System/2* and Compatible Systems _ . . , ■ 100% Gate, Register, and BIOS Level Compatibility with IBM VGA ■ EGA/CGA/MDA BIOS Compatibility

Contextual Info: intJ. 82375EB PCI-EISA Bridge PCEB Provides the Bridge Between the PCI Bus and EISA Bus 32-Bit Data Paths 100% PCI and EISA Compatible — PCI and EISA Master/Slave Interface — Directly Drives 10 PCI Loads and 8 EISA Slots — Supports PCI at 25 MHz to 33 MHz

82378ib

Contextual Info: A P M Ä M ! DM iP© I^[ìfflA'irD@ N] in te i 82378IB SYSTEM I/O SIO Provides the Bridge Between the PCI Bus and ISA Bus Arbitration for PCI Devices — Four PCI Masters are Supported — Fixed, Rotating, or a Combination of the Two 100% PCI and ISA Compatible

Contextual Info: 10 2.5 MIN. C±0. D±0„ B l 0.6 35 PITCH (3. 6) PPUUUIL _ _ 111 In c : n i t : zrai z m z : znj WffllYUUPlYfflS D E TA IL FOR SOLDERING AREA (0.27) VACUUM AREA 5.2 y\UAsAavo (0mm \ HS'G LOCK (SEE TABLE) oonm r t it 0 0 .9 ± 0 .0 5 ~^ y D o o o o p o o o n y d h ~w w

T3D 34 diode

Abstract: 82440LX Diode T3D 57 t57b T27b t59b T31C Transistor t59c ISA BUS spec t119
Contextual Info: E DATASHEET ADDENDUM 82371AB PIIX4 PCI ISA IDE Xcelerator Timing Specifications September 1997 Order Number: 290548-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions

Contextual Info: Features • Fast Read Access Tim e -1 2 0 ns • Dual Voltage Range Operation - Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range • Pin Com patible with JEDEC Standard AT27C4096 • Low Power CMOS Operation - 20 i*A max. less than 1 jiA typical Standby for Vcc = 3.6V

Contextual Info: T27BV040 Features • • • • • • • • • • • Fast Read Access Time -100 ns Unregulated Battery Power Supply Range, 2.7 V to 3.6 V Compatible with JEDEC Standard AT27C040 Low Power CMOS Operation 20 |iA max. Standby 29 mW max. Active at 5 MHz for Vcc = 3.6 V

gi 08d

Contextual Info: QE1M D evice Quad E1 Mapper TXC-04252 DATA SHEET PRODUCT PREVIEW F FEATURES DESCRIPTION • Add/drop four 2.048 Mbit/s signals from an STM-1 VC-4, STS-3/AU-3, or an STS-1 • Independent add and drop bus timing modes • Selectable HDB3 positive/negative rail or NRZ

W89C90

Abstract: CODER MANCHESTER DIFFERENTIAL HAO4 arbiter decoder -1996 w89c901
Contextual Info: Preliminary W89C926 PENTIC+ i.lV in b o n d ^ drHrtP1 E le c tro n ic s C orp . PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER GENERAL DESCRIPTION The W89C926 PENTIC+ is a CMOS device designed for easy implementation ot PCMCIA R2.1 compatible CSMA/CD local area networks. The W89C926 combines a W89C902 Serial LAN

W89C90

Abstract: w89c901 MSA8 valor fl1012 W89C902 hd911 pcmcia ethernet ne2000 EEPROM 93c66 HD11
Contextual Info: Preliminary W89C926 PENTIC+ PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER GENERAL DESCRIPTION The W89C926 PENTIC+ is a CMOS device designed for easy implementation of PCMCIA R2.1 compatible CSMA/CD local area networks. The W89C926 combines a W89C902 Serial LAN

K790

Abstract: K790 9f 0902B
Contextual Info: Features * Fast Read Access Tim e - 90 ns * Dual Voltage Range Operation - Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range * Com patible with JEDEC Standard AT27C020 * Low Power CMOS Operation - 20 pA max. less than 1 |j A typical Standby for Vcc = 3.6V

Contextual Info: Features * Read Access Tim e -1 2 0 ns * Word-wide or Byte-wide Configurable * Dual Voltage Range Operation - Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 1 0 % Supply Range * 8-M egabit Flash and Mask ROM Compatable * Low Power CMOS Operation

sony rxd7

Contextual Info: S O N Y C XD1700 E thernet S w itch Features: ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Fully Integrated Ethernet Switch On A Chip Twenty Four 10Base-X Ports, Two 10/100Base-X Ports All Ports can be either Full or Half Duplex Low Per-Port Cost

tundra scv64

Contextual Info: Table of Contents 1 General Information. 1-1 1.1 Introduction. 1-1 1.2

T55B

Abstract: T71A t19c t17c t61b t58b t57b T27b t65a T3D 62
Contextual Info: 82371AB PCI ISA IDE Xcelerator PIIX4 23.0 Clock, Reset, ISA Bus, X-Bus, and Host Timing Diagrams Figure 41. Clock Timing Period High Time PCICLK, SYSCLK, OSC 2.0V 0.8V Low Time Fall Time Rise Time Figure 42. Reset Inactive Timing SUS_STAT[1:2]# t2f PCIRST#, RSTDRV

Contextual Info: T27BV020 Features • • • • Fast Read Access Time - 85 ns Unregulated Battery Power Supply Range, 2.7 V to 3.6 V Compatible with JEDEC Standard AT27C020 Low Power CMOS Operation 20 |j.A max. Standby 29 mW max. Active at 5 MHz for Vcc = 3.6 V Wide Selection of JEDEC Standard Packages

Contextual Info: Â IW M 1 in te i D M ]F © fô ü iM îrO R !] 82595 ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER Optimal Integration for Lowest Cost Solution — Glueless 8-Bit/ 16-Bit ISA/PCMCIA 2.0 Bus Interface — Provides Fully 802.3 Compliant AUI and TPE Serial Interface

dma controller chip

Contextual Info: in tj, 82374EB EISA SYSTEM COMPONENT ESC • Integrates EISA Compatible Bus Controller — Translates Cycles between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA No Wait State Cycles — Supports Byte Assembly/ Disassembly for 8-, 16- and 32-Bit

intel 82350

Abstract: intel 82352 82351 eisa intel 82357 intel 82358 82359 82350DT EISA Chip Set Design Guide 2LF 1418 82350DT
Contextual Info: in te i 82358DT EISA Bus Controller • Supports 82350 and 82350DT Chip Set Based Systems — Mode Selectable for Either 82350 or 82350DT Based Systems — Mode Defaults to 82350 Based Systems ■ Socket Compatible with the 82358 EISA Bus Controller ■ Provides EISA/ISA Bus Cycle

T27b

Abstract: A1-A16-V
Contextual Info: T27BV010 Features • • • • Fast Read Access Time - 70 ns Unregulated Battery Power Supply Range, 2.7 V to 3.6 V Compatible with JEDEC Standard AT27C010 Low Power CMOS Operation 20 |iA max. Standby 29 mW max. Active at 5 MHz for Vcc = 3.6 V Wide Selection of JEDEC Standard Packages

p54c

Abstract: SiS 85C503 85c501 3-8 decoder 74138 pin diagram 3-8 decoder 74138 85c503 9ROM SiS85C501 SiS chipset T54B
Contextual Info: Pentium/P54C PCI/ISA Chipset 1 85C501/502/503 Overview SiS85C501 SiS85C502 SiS85C503 PCI/ISA Cache Memory Controller PCMC PCI Local Data Buffer (PLDB) PCI System I/O (PSIO) A whole set of the SiS85C501, 85C502, and 85C503 provides fully integrated support for the

GP360

Abstract: RPX 200 GP425 T28b 2d graphics line drawing filling texture mapping CQ T4A X1Y11
Contextual Info: r CIRRUS LOGIC G r aph i cs Primitives: • Trapezoid fill for high speed graphics • Line drawing B it BLT Engine: • Three operand BitBLT source, pattern, and destination • Automatic pattern (texture) replication Page M e mo r y Interface: • XY to linear page memory address calculation

2SA138

Abstract: st28c ge 142 2S160 RBL 43 P ST28B 2S156 ST28A RBL 43 P TRANSISTOR 2S153
Contextual Info: 5 - - FOR U SE BY E L E C T R IC IA N S O V E R S E A S : •M-EiiOSWHE New Transistor Manual lists all the transistors registered with the Electronic Industries Association of Japan (EIAJ), arranged in a manner easy to look up. We hope that you will make full use of the data provided in this manual by referring to the Japanese-English