T20D Search Results

Contextual Info: M ICRON 512K DRAM MODULE 512K - - Ä IV I W U X X T20D51240 40 DRAM MODULE 40 DRAM FAST-PAGE-MODE (T20D51240 LOW POWER, FEXTENDED Y T F N n F n RF REFRESH (T20D51240 L) l - L . FEATURES • • • • • • • OPTIONS 72-Pin SIMM (DE-14) M T20D51240G

ibex

Abstract: bay microsystems
Contextual Info: PRODUCT BRIEF IBEx T20d Dual 10G SONET/SDH/OTN Demarcation HIGHLIGHTS IBEx T20d 1 OC-192/OTU2 2 3 OC-192/OTU2 OC-192/OTU2 2 OC-192/OTU2 1 OC-192/OTU2 OC-192/OTU2 OC-192/OTU2 OC-192/OTU2 3 IBEx T20d The IBEx T20d transport demarcation platform utilizes Bay Microsystems’

ic ns 4263

Contextual Info: MICRON 512K □PAM M O n ill m V U U U 51 2K _ X X T20D51240 40 DRAM MODULE 40 DRAM FAST-PAGE-MODE T20D51240 LOW POWER, EXTENDED REFRESH (T20D51240 L) F L . FEATURES • • • • • • • OPTIONS M T20D 51240G • Packages Leadless 7 2 -pin SIM M (gold)

T20D201

Abstract: gt20d201
Contextual Info: TOSHIBA T20D201 Insulated Gate Bipolar Transistor U nit in m m Silicon P Channel MOS Type High Power Amplifier Application Features • High Breakdown Voltage - VCES = -250V Min • High Forward Transfer Admittance - Yfs' = 10S (Typ.) • Complementary to T20D101

16C450

Abstract: MS-018 PC16552 PC16C552 PLCC44 SC16C2552B SC16C2552BIA44 ST16C2552
Contextual Info: SC16C2552B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s max. , with 16-byte FIFOs Rev. 03 — 12 February 2009 Product data sheet 1. General description The SC16C2552B is a two channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel

SMD T6s

Abstract: 16C450 16C550 HVQFN24 MO-220 SC16C750B SC16C751BIBS
Contextual Info: SC16C751B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs Rev. 02 — 10 October 2008 Product data sheet 1. General description The SC16C751B is a Universal Asynchronous Receiver and Transmitter UART used for serial data communications. Its principal function is to convert parallel data into serial

Contextual Info: TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com QUAD UARTS WITH 64-BYTE FIFO Check for Samples: TL16CP754C, TL16C754C FEATURES 1 • • • • • • • • • • • • • ST16C654/654D Pin Compatible With Additional Enhancements

82430LX

Contextual Info: in te * 82433LX/82433NX LOCAL BUS ACCELERATOR LBX Supports th e Full 64-bit Pentium- Processor Data Bus at Frequencies up to 66 MHz (82433LX and 82433NX) Dual-Port Architecture Allows Concurrent Operations on the Host and PCI Buses Drives 3.3V Signal Levels on the CPU

intel 775 motherboard diagram

Abstract: intel 830 mobile MOTHERBOARD CIRCUIT diagram pentium 298340 Pentium M 82801CAM 82830MP Pentium III Developer intel 1401
Contextual Info: R Mobile Intel Pentium III Processor–M Datasheet July 2001 Order Number: 298340-001 ® Mobile Intel Pentium III Processor-M Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

Contextual Info: XR16C864 Preliminary Information QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO DESCRIPTION The XR16C864*1 864 is a universal asynchronous receiver and transmitter (UART) with a dual foot print interface compatible with the ST16C554/654 and ST68C554. The 864 is an enhanced UART with 128 byte FIFO’s,

Contextual Info: XR16C854 Preliminary Information QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO DESCRIPTION The XR16C854 *1 854 is a universal asynchronous receiver and transmitter (UART) with a dual foot print interface compatible with the ST16C554D/654 and ST68C554/654. The 854 is an enhanced UART with 128 byte

ST16C450

Contextual Info: ST16C450 -UART with Higher Operating Speed and Lower Access Time HomeNewsCareers Investor Relations Contact Us PartnerNet Login Search CommunicationsInterfacePower Management ST16C450 Support Info Request How to Order Samples How to Buy Print this page UART with Higher Operating Speed and Lower Access Time

16c550

Abstract: 30035 marking t9d 16C450 LQFP64 PLCC44 SC16C750 SC16C750IA44 SC16C750IB64 TL16C750
Contextual Info: SC16C750 Universal Asynchronous Receiver/Transmitter UART with 64-byte FIFO Rev. 04 — 20 June 2003 Product data 1. General description The SC16C750 is a Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into

Eden ESP 4000

Abstract: x86 family 15 model 2 stepping 7 VIA C3 Samuel 2 Processor VIA Eden esp 4000 EDEN ESP winchip x86 processor architecture VIA Eden esp6000 EDEN
Contextual Info: VIA Eden TM Embedded System Platform Processor Datasheet Preliminary Information VIA Eden ESP Processor Datasheet Preliminary Information January 2002 This is Version 1.15 of the VIA Eden ESP Processor Datasheet. 2002 VIA Technologies, Inc All Rights Reserved.

SC16C750B

Abstract: 2006-17 16C450 marking t9d HVQFN32 LQFP64 PLCC44 SC16C750 TL16C750 41DSR
Contextual Info: SC16C750B 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs Rev. 04 — 25 August 2006 Product data sheet 1. General description The SC16C750B is a Universal Asynchronous Receiver and Transmitter UART used for serial data communications. Its principal function is to convert parallel data into serial

SC16C650B

Abstract: marking t9d Code T6H Code T6S 16C450 DIP40 HVQFN32 LQFP48 PLCC44 ST16C650A
Contextual Info: SC16C650B 5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared IrDA encoder/decoder Rev. 03 — 10 December 2004 Product data 1. General description The SC16C650B is a Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data

Contextual Info: TL16CP754C, TL16C754C SLLS644G – DECEMBER 2007 – REVISED MAY 2011 www.ti.com QUAD UARTS WITH 64-BYTE FIFO Check for Samples: TL16CP754C, TL16C754C FEATURES 1 • • • • • • • • • • • • • ST16C654/654D Pin Compatible With Additional Enhancements

C1994

Contextual Info: ADVANCE M IC R O N I T20D840 8 MEG X 40 DRAM MODULE 8 MEG X 40 DRAM DRAM MODULE FAST PAGE MODE FEATURES Industry-standard 72-pin single in-line package High-perform ance CMOS silicon-gate process Single 5V ±10% pow er supply All device pins are TTL-compatible

Contextual Info: M IC R O N 512K 512K X T20D51240 40 DRAM MODULE 40 DRAM FAST PAGE MODE T20D51240 LOW POWER, EXTENDED REFRESH (T20D51240 L) FEATURES • • • • • • • • • PIN ASSIGNMENT (Top View) 72-pin single-in-line package High-performance, CMOS silicon-gate process.

ST10

Abstract: ST10R172L st10 Bootstrap
Contextual Info: ST10R172L 16-BIT LOW VOLTAGE ROMLESS MCU DATASHEET • High Performance 16-bit CPU ● ● ● ● ● ● ● ● ■ ● ● ● ● ● OSC WDT Programmable external bus characteristics for different address ranges 8-bit or 16-bit external data bus Multiplexed or demultiplexed external

DIP40

Abstract: INS8250 LQFP48 PLCC44 SC16C2550B SC16C2550BIA44 SC16C2550BIN40 SC16C550 ST16C2550
Contextual Info: SC16C2550B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s max. , with 16-byte FIFOs Rev. 01 — 29 March 2004 Product data 1. Description The SC16C2550B is a two channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to

ST16C450

Abstract: icl 7017 icl 7017 datasheet ST16C450IP40 ST16C450IQ48 16C450 NS16450 ST16C450CJ44 ST16C450CP40 ST16C450CQ48
Contextual Info: ST16C450 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER UART September 2003 GENERAL DESCRIPTION D4 D3 D2 D1 D0 N.C. VCC -RI -CD -DSR -CTS 6 5 4 3 2 1 44 43 42 41 40 PLCC Package D5 7 39 RESET D6 8 38 -OP1 D7 9 37 -DTR RCLK 10 36 -RTS RX 11 35 -OP2 N.C. 12 34

TL16C2550

Abstract: TL16C752C TL16C752CPFB TL16C752CRHB
Contextual Info: TL16C752C DUAL UART WITH 64-BYTE FIFO www.ti.com SLLS646 – MARCH 2008 FEATURES 1 • • • • • • • • • • • • • ST16C654/654D Pin Compatible With Additional Enhancements PFB Package Only Supports up to 24-MHz Crystal Input Clock (1.5 Mbps)

MT4C4001

Contextual Info: T20D240 2 MEG X 40 DRAM M ODULE p iC R O fS J 2 MEG X 40 DRAM DRAM MODULE NEW I FAST PAGE MODE T20D240 LOW POWER, EXTENDED REFRESH (T20D240 L) FEATURES • • • • PIN ASSIGNMENT (Top View) 72-pin single-in-line package High-performance CM OS silicon-gate process.