SUM16 Search Results

SUM16N20-125

Abstract: DS 1287
Contextual Info: SPICE Device Model SUM16N20-125 Vishay Siliconix N-Channel 200-V D-S , 175°C MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Model Subcircuit) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range

SUM16N20-125

Contextual Info: SUM16N20-125 New Product Vishay Siliconix N-Channel 200-V D-S 175_C MOSFET FEATURES D D D D PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (W) 200 ID (A) 0.125 @ VGS = 10 V 16 0.150 @ VGS = 6 V 14.6 TrenchFETr Power MOSFETS 175_C Junction Temperature New Low Thermal Resistance Package

Contextual Info: SUM16N20-125 New Product Vishay Siliconix N-Channel 200-V D-S 175_C MOSFET FEATURES D D D D PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (W) 200 ID (A) 0.125 @ VGS = 10 V 16 0.150 @ VGS = 6 V 14.6 TrenchFETr Power MOSFETS 175_C Junction Temperature New Low Thermal Resistance Package

SUM16N20-125

Contextual Info: SUM16N20-125 New Product Vishay Siliconix N-Channel 200-V D-S 175_C MOSFET FEATURES D D D D PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (W) 200 ID (A) 0.125 @ VGS = 10 V 16 0.150 @ VGS = 6 V 14.6 TrenchFETr Power MOSFETS 175_C Junction Temperature New Low Thermal Resistance Package

Contextual Info: SUM16N20-125 New Product Vishay Siliconix N-Channel 200-V D-S 175_C MOSFET FEATURES D D D D PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (W) 200 ID (A) 0.125 @ VGS = 10 V 16 0.150 @ VGS = 6 V 14.6 TrenchFETr Power MOSFETS 175_C Junction Temperature New Low Thermal Resistance Package

SUM16N20-125

Contextual Info: SUM16N20-125 New Product Vishay Siliconix N-Channel 200-V D-S 175_C MOSFET FEATURES D D D D PRODUCT SUMMARY V(BR)DSS (V) rDS(on) (W) 200 ID (A) 0.125 @ VGS = 10 V 16 0.150 @ VGS = 6 V 14.6 TrenchFETr Power MOSFETS 175_C Junction Temperature New Low Thermal Resistance Package

lfxp2-40e

Abstract: LVCMOS25 LD48 LFXP2-17E-5FTN256C HB1004 ispLEVER project Navigator route place LFXP2-5E-5QN IPUG35 LFXP2-8E
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.9, May 2011 LatticeXP2 Family Handbook Table of Contents May 2011 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

Contextual Info: LF43891 9 x 9-b it D igital Filter FEATURES_ □ 30 M H z M axim um Sam pling Rate □ 240 M H z M ultiply-Accumulate Rate □ 8 Filter Cells □ 8-bit U nsigned or 9-bit Tw o's C om plem ent Data □ 8-bit U nsigned or 9-bit Tw o's C om plem ent Coefficients

Contextual Info: LF43891 9 x 9-bit Digital Filter D E V IC E S IN C O R P O R A T E D □ □ □ □ 40 MHz Maximum Sampling Rate 320 MHz Multiply-Accumulate Rate 8 Filter Cells 8-bit Unsigned or 9-bit Two's Complement Data/Coefficients □ 26-bit Data Outputs □ Shift-and-Add Output Stage for

Contextual Info: H A RR IS S E M I C O N D SE CT OR ’ ••'E: d 4305271 D 0 m i4M0 4 H S P 43481 HARRIS PRELIMINARY Digital Filter January 1989 Features Description • Four Filter Cells The HSP43481 is a video-speed Digital Filter DF designed to efficiently implement vector operations such as

Contextual Info: HSP43168/883 Data Sheet May 1999 Dual FIR Filter Features The HSP43168/883 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR

Contextual Info: HSP43881/883 Data Sheet May 1999 File Num ber 2449.4 Digital Filter Features The HSP43881/883 is a video speed Digital Filter DF designed to efficiently implem ent vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded

Contextual Info: HSP43891/883 ¡33 Digital Filter Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • 0MHz to 25.6MHz Sample Rate • Eight Filter Cells • 9-Bit Coefficients and Signal Data

F10-C2

Abstract: SUM22
Contextual Info: HSP43881/883 TM Data Sheet May 1999 FN2449.4 Digital Filter Features The HSP43881/883 is a video speed Digital Filter DF designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single

vhdl code for 4 bit ripple carry adder

Abstract: VHDL code for 16 bit ripple carry adder 32 bit carry adder vhdl code vhdl code of ripple carry adder vhdl code for full adder EQCOMP12 32 bit ripple carry adder vhdl code vhdl code comparator
Contextual Info: fax id: 6434 Back Efficient Arithmetic Designs With Cypress CPLDs Introduction This application note is intended to provide designers with some insight into efficient means of implementing arithmetic functions in Cypress CPLDs. Additionally this application note

Contextual Info: LE43R91 zi;»-«- mm LF43891 9 x 9-bit Digital Filter DEVICES INCORPORATED FEATURES □ □ □ □ DESCRIPTION 40 MHz Maximum Sampling Rate 320 MHz Multiply-AccumulateRate 8 Filter Cells 8-bit Unsigned or 9-bit Two's Complement Data □ 8-bit Unsigned or 9-bit Two's

1781-oa5s

Abstract: 1781-IA5S 1781-0A5S 1770-T1 uPC 577H 2760-RB 1781-IB5S 1771-DA PLC based fire alarm system RS-485/lan cable cut
Contextual Info: ALLEN-BRADLEY Bulletin 2755 High Speed Decoder Catalog Numbers 2755-DM9 & -DM9E User Manual Important User Information Solid state equipment has operational characteristics differing from those of electromechanical equipment. “Safety Guidelines for the Application,

HSP43168

Abstract: circuit diagram for FIR filter B910
Contextual Info: HSP43168/883 TM Data Sheet May 1999 FN3177.3 Dual FIR Filter Features The HSP43168/883 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR

Contextual Info: i l l H A R R IS H S P 4 3 8 8 1 Digital Filter A u gu st 1 9 9 2 Features Description • Eight Filter Cells The HSP43881 is a video speed Digital Filter DF designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells

multiplier accumulator MAC code verilog

Abstract: multiplier accumulator MAC code VHDL algorithm MULT18X18 ispLEVER project Navigator b312 diode SUM30 SUM32 TN1057 vhdl code for floating point subtractor ieee floating point multiplier verilog
Contextual Info: LatticeECP-DSP sysDSP Usage Guide October 2005 Technical Note TN1057 Introduction This technical note discusses how to access the features of the LatticeECP -DSP sysDSP™ Digital Signal Processing Block described in the LatticeECP/EC Family data sheet. Designs targeting the sysDSP Block offer significant improvement over traditional LUT-based implementations. Table 14-1 provides an example of the

Contextual Info: h * 8 HSP43 481/883 Digital Filter August 1992 Description Features • This C ircuit Is Processed in accordance to M il-S td -8 8 3 C and Is Fully C onform ant Paragraph 1.2.1 U nd er th e Provisions of • 0 to 25 .6 M H z S am ple Rate • Four Filter Cells

Contextual Info: HSP43 891/883 h a r r is D igital Filter A ugust 1 9 9 2 Features Description • This C ircuit is P rocessed In A ccordance to M il-S td -8 8 3 C and is Fully C onform ant Paragraph 1.2.1 U nd er the Provisions of • 0 to 25 .6 M H z S am ple Rate • Eight Filter Cells

ISA CODE VHDL

Abstract: 16x4 ram VERILOG IPUG35
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.3, January 2009 LatticeXP2 Family Handbook Table of Contents January 2009 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

prbs pattern generator using vhdl

Abstract: BUT16
Contextual Info: LatticeECP2/M Family Handbook HB1003 Version 04.9, April 2011 LatticeECP2/M Family Handbook Table of Contents April 2011 Section I. LatticeECP2/M Family Data Sheet Introduction Features . 1-1