SUM10 Search Results

Contextual Info: SUM100N12–14L New Product Vishay Siliconix N-Channel 125-V D-S MOSFET FEATURES PRODUCT SUMMARY rDS(on) (W) ID (A)a 0.0144 @ VGS = 10 V 100 0.0154 @ VGS = 4.5 V 96 VDS (V) 125 D TrenchFETr Power MOSFET D 100% Rg Tested Qg (Typ) APPLICATIONS 67 nC COMPLIANT

Contextual Info: SUM60UF thru SUM100UF and SUM60UFSMS thru SUM100UFSMS Solid State Devices, Inc. 14701 Firestone Blvd * La Mirada, Ca 90638 Phone: 562 404-4474 * Fax: (562) 404-1773 ssdi@ssdi-power.com * www.ssdi-power.com Designer’s Data Sheet Part Number/Ordering Information

sum100n12

Contextual Info: SUM100N12-14L Vishay Siliconix New Product N-Channel 125-V D-S MOSFET FEATURES PRODUCT SUMMARY rDS(on) (W) ID (A)a 0.0144 @ VGS = 10 V 100 0.0154 @ VGS = 4.5 V 96 VDS (V) 125 D TrenchFETr Power MOSFET D 100% Rg Tested Qg (Typ) APPLICATIONS 67 nC COMPLIANT

73400

Contextual Info: SUM100N12–14L New Product Vishay Siliconix N-Channel 125-V D-S MOSFET FEATURES PRODUCT SUMMARY rDS(on) (W) ID (A)a 0.0144 @ VGS = 10 V 100 0.0154 @ VGS = 4.5 V 96 VDS (V) 125 D TrenchFETr Power MOSFET D 100% Rg Tested Qg (Typ) APPLICATIONS 67 nC COMPLIANT

RC0037

Abstract: RC0037E
Contextual Info: SUM60F thru SUM100F and SUM60FSMS thru SUM100FSMS Solid State Devices, Inc. 14701 Firestone Blvd * La Mirada, Ca 90638 Phone: 562 404-4474 * Fax: (562) 404-1773 ssdi@ssdi-power.com * www.ssdi-power.com 500 mA FAST RECOVERY RECTIFIER 6,000 thru 10,000 VOLTS

SUM100N12-14L

Contextual Info: SPICE Device Model SUM100N12-14L Vishay Siliconix N-Channel 125-V D-S MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range

RC0039A

Abstract: SUM60UF SUM70UF SUM80UF SUM90UF
Contextual Info: SUM60UF & UFSMS thru SUM100UF & UFSMS PRELIMINARY SOLID STATE DEVICES, INC. 14830 Valley View Blvd * La Mirada, Ca 90638 Phone: 562 404-7855 * Fax: (562) 404-1773 0.4 AMPS 6000 - 10000 VOLTS 60 nsec HIGH VOLTAGE ULTRA FAST RECTIFIER 1.30 Designer's Data Sheet

DSA00384671

Contextual Info: SUM100N12–14L New Product Vishay Siliconix N-Channel 125-V D-S MOSFET FEATURES PRODUCT SUMMARY rDS(on) (W) ID (A)a 0.0144 @ VGS = 10 V 100 0.0154 @ VGS = 4.5 V 96 VDS (V) 125 D TrenchFETr Power MOSFET D 100% Rg Tested Qg (Typ) APPLICATIONS 67 nC COMPLIANT

Contextual Info: SUM60F & FSMS thru SUM100F & FSMS PRELIMINARY SOLID STATE DEVICES, INC. 14830 Valley View Blvd * La Mirada, Ca 90638 Phone: 562 404-7855 * Fax: (562) 404-1773 0.5 AMPS 6000 - 10000 VOLTS 180 nsec HIGH VOLTAGE RECTIFIER 1.30 Designer's Data Sheet FEATURES:

Contextual Info: SUM100N12–14L New Product Vishay Siliconix N-Channel 125-V D-S MOSFET FEATURES PRODUCT SUMMARY rDS(on) (W) ID (A)a 0.0144 @ VGS = 10 V 100 0.0154 @ VGS = 4.5 V 96 VDS (V) 125 D TrenchFETr Power MOSFET D 100% Rg Tested Qg (Typ) APPLICATIONS 67 nC COMPLIANT

Contextual Info: SK4225 POSfTROMC N H IS IR E S 6QJEVE5 THE DATA ON THIS DRMVM6 TO BE RELIABLE, SM CE THE TECHNICAL INFORMATION IS QNEN FREE OF CHARGE. THE USER EMPLOYS SUCH INFORMATION AT H IS OWN D6CREI10N AND R SK . POSITRONIC M DÜSTRES ASSUMES NO R E SP O N SIB L E FOR RESULTS OBTAINED OR DAMAGES

SK4224

Contextual Info: SK4224 DATE RET 3=11 W NC POSTTROMC M D U 5IR ES BELEVES THE DATA ON THB DRMflNG TO BE RELMBLE, SR C E THE TECHNICAL INFORMATION IS QNEN FREE OF CHARGE. THE USER EMPLOYS SUCH INFORMATION AT H IS OWN D6CRET10N AND R 6K. POSITRON1C M D U SÏR ES ASSUMES NO R E SP O N SIB L E FOR RESULTS OBTAINED OR DAMAGES

lfxp2-40e

Abstract: LVCMOS25 LD48 LFXP2-17E-5FTN256C HB1004 ispLEVER project Navigator route place LFXP2-5E-5QN IPUG35 LFXP2-8E
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.9, May 2011 LatticeXP2 Family Handbook Table of Contents May 2011 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

Contextual Info: LF43891 9 x 9-b it D igital Filter FEATURES_ □ 30 M H z M axim um Sam pling Rate □ 240 M H z M ultiply-Accumulate Rate □ 8 Filter Cells □ 8-bit U nsigned or 9-bit Tw o's C om plem ent Data □ 8-bit U nsigned or 9-bit Tw o's C om plem ent Coefficients

Broken Conductor Detection for Overhead Line Distribution System

Abstract: verilog code for CORDIC to generate sine wave verilog code for cordic algorithm for wireless la TXC 13.56 sma diode h5c intel 945 motherboard schematic diagram 2005Z fet k241 EARTH LEAKAGE RELAY diagram schematic diagram for panasonic inverter air cond
Contextual Info: Stratix GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com SGX5V1-1.2 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

logic diagram to setup adder and subtractor

Abstract: EP1C12
Contextual Info: 2. Cyclone Architecture C51002-1.6 Functional Description Cyclone devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and

Contextual Info: HSP43168/883 Data Sheet May 1999 Dual FIR Filter Features The HSP43168/883 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR

Contextual Info: HSP43881/883 Data Sheet May 1999 File Num ber 2449.4 Digital Filter Features The HSP43881/883 is a video speed Digital Filter DF designed to efficiently implem ent vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded

EP1C6 equivalent

Abstract: 100 PIN tQFP ALTERA DIMENSION c 5929 hot MA-2395 ps1784
Contextual Info: Cyclone FPGA Family March 2003, ver. 1.1 Introduction Preliminary Information Features. Data Sheet The CycloneTM field programmable gate array family is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic elements LEs and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR)

F10-C2

Abstract: SUM22
Contextual Info: HSP43881/883 TM Data Sheet May 1999 FN2449.4 Digital Filter Features The HSP43881/883 is a video speed Digital Filter DF designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single

i2c isolator

Contextual Info: 19-5192; Rev 0; 6/10 TION KIT EVALUA BLE AVAILA 12-Channel, High-Voltage Sensor, Smart Data-Acquisition Interface The MAX11068 is a programmable, highly integrated, high-voltage, 12-channel, battery-monitoring smart dataacquisition interface. It is optimized for use with batteries used in automotive systems, hybrid electric battery

EP1S60

Abstract: "Single-Port RAM"
Contextual Info: Chapter 1. Introduction S51001-3.1 Introduction The Stratix family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities of up to 79,040 logic elements LEs and up to 7.5 Mbits of RAM. Stratix devices offer up to 22 digital signal

diode jd 4.7-16

Abstract: MA4001
Contextual Info: Stratix Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com S5V1-1.2 Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

Contextual Info: LatticeECP/EC Family Handbook HB1000 Version 03.7, September 2012 LatticeECP/EC Family Handbook Table of Contents September 2012 Section I. LatticeECP/EC Family Data Sheet Introduction Features . 1-1