SOT996 Search Results

Contextual Info: Package outline XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm B D SOT996-2 A E A A1 detail X terminal 1 index area e1 1 4 8 5 C C A B C v w b e L1 y y1 C L2 L X 1 2 mm scale Dimensions mm are the original dimensions

Contextual Info: Reflow soldering footprint 2.400 pa + oa 2.000 0.500 0.500 0.250 0.025 0.025 4.250 3.400 pa + oa 2.000 4.000 0.900 www.nxp.com 2009 NXP B.V. solder lands placement area solder paste occupied area Dimensions in mm sot996-2_fr All rights reserved. Reproduction in whole or in part is prohibited without prior consent of the copyright owner. The information presented in this document does not

Contextual Info: Reflow soldering footprint Footprint information for reflow soldering of XSON8 package SOT996-3 Hx Gx P D P1 0.025 0.025 Hy By Gy Ay B solder lands placement area solder paste occupied area DIMENSIONS in mm P P1 Ay By B D Gx Gy Hx Hy 0.5 0.5 4 2 0.9 0.25 2

Contextual Info: Package outline XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm e1 C C A B C v w b SOT996-3 y y1 C e 1 4 L L1 terminal 1 index area 8 5 X A B D E A A1 A3 detail X terminal 1 index area 1 Dimensions Unit 1 max

Contextual Info: XS ON 8U SOT996-2 XSON8 U ; Reel pack, Reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or H Ordering code (12NC) ending 125 Rev. 5 — 2 May 2013 Packing information 1. Packing method Printed plano box Barcode label Reel

NXP 12NC ending

Abstract: SOT996-2 SOT996 SOT99
Contextual Info: SOT996-2 Reversed product orientation 12NC ending 125 Rev. 02 — 24 April 2009 Packing information 1. Packing method Fig. 1 Package version 12NC ending Reel dimensions d x w mm SPQ/PQ (pcs) Reels per box Outer box dimensions l x w x h (mm) SOT996-2 125

nz104

Contextual Info: 74LVC2G66 Bilateral switch Rev. 7 — 22 June 2012 Product data sheet 1. General description The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each switch has two input/output terminals nY and nZ and an active HIGH enable input (nE).

MARKING V7 6-PIN

Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 11 — 6 July 2012 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

PA9540

Abstract: PA9540B
Contextual Info: PCA9540B 2-channel I2C-bus multiplexer Rev. 04 — 3 September 2009 Product data sheet 1. General description The PCA9540B is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus. The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.

Marking code V7

Contextual Info: 74LVC2G00 Dual 2-input NAND gate Rev. 11 — 22 June 2012 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

74AHC3GU04

Abstract: 74AHC3GU04DC 74AHC3GU04DP 74AHC3GU04GM JESD22-A114E MO-187
Contextual Info: 74AHC3GU04 Inverter Rev. 03 — 26 January 2009 Product data sheet 1. General description The 74AHC3GU04 is a high-speed Si-gate CMOS device. This device provides the inverting single stage function. 2. Features • Symmetrical output impedance ■ High noise immunity

74AHC2G08

Abstract: 74AHC2G08DC 74AHC2G08DP 74AHCT2G08 74AHCT2G08DC 74AHCT2G08DP JESD22-A114E
Contextual Info: 74AHC2G08; 74AHCT2G08 Dual 2-input AND gate Rev. 03 — 12 January 2009 Product data sheet 1. General description The 74AHC2G08; 74AHCT2G08 is a high-speed Si-gate CMOS device. The 74AHC2G08; 74AHCT2G08 provides two 2-input AND gates. 2. Features • Symmetrical output impedance

JESD22-A114E

Abstract: NX3L1G53GD NX3L1G53GM NX3L1G53GT
Contextual Info: NX3L1G53 Low-ohmic single-pole double-throw analog switch Rev. 03 — 17 April 2009 Product data sheet 1. General description The NX3L1G53 provides one low-ohmic single-pole double-throw analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. It has a digital select input S ,

74LVC1G53

Abstract: 74LVC1G53DC 74LVC1G53DP 74LVC1G53GD 74LVC1G53GT JESD22-A114E MO-187 V53 TSSOP8
Contextual Info: 74LVC1G53 2-channel analog multiplexer/demultiplexer Rev. 05 — 11 June 2008 Product data sheet 1. General description The 74LVC1G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device. The 74LVC1G53 provides one analog multiplexer/demultiplexer with a digital select

74AUP2G125

Abstract: 74AUP2G125DC 74AUP2G125GT JESD22-A114E JESD78
Contextual Info: 74AUP2G125 Low-power dual buffer/line driver; 3-state Rev. 05 — 2 February 2009 Product data sheet 1. General description The 74AUP2G125 provides the dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE

74LVC3G14

Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187
Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 07 — 12 June 2008 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger action. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

74HC2G32

Abstract: 74HC2G32DC 74HC2G32DP 74HCT2G32 74HCT2G32DC 74HCT2G32DP JESD22-A114E
Contextual Info: 74HC2G32; 74HCT2G32 Dual 2-input OR gate Rev. 03 — 12 May 2009 Product data sheet 1. General description The 74HC2G32 and 74HCT2G32 are high-speed Si-gate CMOS devices. They provide two 2-input OR gates. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.

VSSOP8

Abstract: 74HC3GU04 74HC3GU04DC 74HC3GU04DP JESD22-A114E MO-187
Contextual Info: 74HC3GU04 Inverter Rev. 03 — 11 May 2009 Product data sheet 1. General description The 74HC3GU04 is a high-speed Si-gate CMOS device. This device provides three inverter gates with unbuffered outputs. The 74HC3GU04 has CMOS input switching levels and supply voltage range 2 V to 6 V.

74AVCH2T45

Abstract: 74AVCH2T45DC 74AVCH2T45GT JESD22-A114E
Contextual Info: 74AVCH2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 03 — 6 May 2009 Product data sheet 1. General description The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports nA and nB , a direction control input

74AHC3G04

Abstract: 74AHC3G04DC 74AHC3G04DP 74AHCT3G04 74AHCT3G04DC 74AHCT3G04DP JESD22-A114E
Contextual Info: 74AHC3G04; 74AHCT3G04 Inverter Rev. 02 — 26 January 2009 Product data sheet 1. General description The 74AHC3G04; 74AHCT3G04 is a high-speed Si-gate CMOS device. The 74AHC3G04; 74AHCT3G04 provides three inverting buffers. 2. Features • Symmetrical output impedance

74LVC2G66

Abstract: 74LVC2G66DC 74LVC2G66DP 74LVC2G66GT 74LVCV2G66 JESD22-A114E JESD78
Contextual Info: 74LVC2G66 Bilateral switch Rev. 04 — 1 July 2008 Product data sheet 1. General description The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each switch has two input/output terminals nY and nZ and an active HIGH enable input (nE).

74LVC2G126

Abstract: 74LVC2G126DC 74LVC2G126DP 74LVC2G126GD 74LVC2G126GM 74LVC2G126GT JESD22-A114E MO-187
Contextual Info: 74LVC2G126 Dual bus buffer/line driver; 3-state Rev. 08 — 5 May 2008 Product data sheet 1. General description The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each 3-state output is controlled by an output enable input pin nOE . A LOW-level at pin nOE

74AUP2G240

Abstract: 74AUP2G240DC 74AUP2G240GT JESD22-A114E JESD78
Contextual Info: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 03 — 7 April 2009 Product data sheet 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE

74LVC2G241

Abstract: 74LVC2G241DC 74LVC2G241DP 74LVC2G241GD 74LVC2G241GM 74LVC2G241GT JESD22-A114E
Contextual Info: 74LVC2G241 Dual buffer/line driver; 3-state Rev. 09 — 10 June 2008 Product data sheet 1. General description The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE: