74LVC3G14GT Search Results
74LVC3G14GT Datasheets (5)
Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
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74LVC3G14GT |
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Triple inverting Schmitt trigger with 5 V tolerant input | Original | 81.27KB | 17 | ||
74LVC3G14GT,115 |
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74LVC3G14 - IC LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8, 1 X 1.95 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT833-1, XSON-8, Gate | Original | 303.13KB | 23 | ||
74LVC3G14GT,115 |
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Triple inverting Schmitt trigger with 5 V tolerant input; Package: SOT833-1 (XSON8U); Container: Reel Pack, SMD, 7" | Original | 97.87KB | 18 | ||
74LVC3G14GT-G |
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74LVC3G14GT - Triple inverting Schmitt trigger with 5 V tolerant input | Original | 303.13KB | 23 | ||
74LVC3G14GT-G |
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Triple inverting Schmitt trigger with 5 V tolerant input | Original | 97.87KB | 18 |
74LVC3G14GT Price and Stock
Nexperia 74LVC3G14GT,115IC INVERT SCHMITT 3CH 3INP 8XSON |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74LVC3G14GT,115 | Digi-Reel | 4,622 | 1 |
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74LVC3G14GT,115 | Reel | 12 Weeks | 10,000 |
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74LVC3G14GT,115 | 6,006 |
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74LVC3G14GT,115 | 70,890 | 3,871 |
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74LVC3G14GT,115 | 3,512 | 1,631 |
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74LVC3G14GT,115 | 120,890 | 1 |
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74LVC3G14GT,115 | Reel | 5,000 |
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74LVC3G14GT,115 | 12 Weeks | 10,000 |
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74LVC3G14GT,115 | 14 Weeks | 5,000 |
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74LVC3G14GT,115 | 14 Weeks | 5,000 |
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NXP Semiconductors 74LVC3G14GT,115Inverter Schmitt Trigger 3-Element CMOS 8-Pin XSON T/R |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74LVC3G14GT,115 | 60,000 | 3,871 |
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74LVC3G14GT,115 | 71,369 | 1 |
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74LVC3G14GT Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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MARKING V7 6-PINContextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 11 — 6 July 2012 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. |
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74LVC3G14 74LVC3G14 MARKING V7 6-PIN | |
74LVC3G14
Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187
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74LVC3G14 74LVC3G14 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187 | |
Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 12 — 9 April 2013 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. |
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74LVC3G14 74LVC3G14 | |
74LVC3G14
Abstract: NC7NP14L8X NC7NP14 NC7NZ14 SN74AUP3G14 SN74LVC3G14 74lvc3g14dp sn74lvc3g14dcur NC7NZ14L8X
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SLG74LB3G14 000-0074LB3G14-10 74LVC3G14 NC7NP14L8X NC7NP14 NC7NZ14 SN74AUP3G14 SN74LVC3G14 74lvc3g14dp sn74lvc3g14dcur NC7NZ14L8X | |
74lvc3g14
Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT
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74LVC3G14 74LVC3G14 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT | |
74LVC3G14
Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187
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74LVC3G14 74LVC3G14 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187 | |
Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 9 — 22 September 2011 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. |
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74LVC3G14 74LVC3G14 | |
Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 10 — 23 November 2011 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. |
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74LVC3G14 74LVC3G14 | |
is 14543
Abstract: 14543 74LVC3G14 74LVC3G14DC 74LVC3G14DP 74LVC3G14GT MO-187
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74LVC3G14 74LVC3G14 is 14543 14543 74LVC3G14DC 74LVC3G14DP 74LVC3G14GT MO-187 | |
74LVC3G14
Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187
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74LVC3G14 74LVC3G14 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187 | |
Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 04 — 14 March 2007 Product data sheet 1. General description The 74LVC3G14 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL-families. |
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74LVC3G14 74LVC3G14 |