SEP30 Search Results

E89556

Contextual Info: bq48SH-28x6 SLUS508A – DECEMBER 2001 REVISED – JUNE 2002 SNAPHAT WITH INTEGRATED BATTERY AND CRYSTAL FEATURES D Detachable Unit Allowing Replacement D Integrated 6-pF Watch Crystal for Real-Time D D D D DESCRIPTION Clock Operation Integrated Lithium Coin Cell for Nonvolatile

Contextual Info: 74ACT11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS013C – AUGUST 1987 – REVISED APRIL 1996 D D D, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted

EV2200-40

Abstract: PCB design layout of gas leakage alarm
Contextual Info: bq2040 Gas Gauge IC With SMBus Interface Features General Description ➤ Provides accurate measurement of available charge in NiCd, NiMH, and Li-Ion batteries The bq2040 Gas Gauge IC With SMBus Interface is intended for battery-pack or in-system installation to maintain an accurate record

Contextual Info: 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCAS007C – JULY 1987 – REVISED APRIL 1996 D D D D D, DB, OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process

SLUA099

Contextual Info: bq24004 bq24005 bq24006 www.ti.com SLUS476B – DECEMBER 2000 – REVISED MAY 2002 TWO-CELL Li-ION CHARGE MANAGEMENT IC FOR PDAs AND INTERNET APPLIANCES FEATURES D Highly Integrated Solution With FET Pass Transistor and Reverse-Blocking Schottky and Thermal Protection

Contextual Info: ICs for TV AN5829S Sound multiplex decoder IC for the U.S. televisions • Overview M Di ain sc te on na tin nc ue e/ d The AN5829S is a multiplex sound demodulation IC dedicated to the U.S. television and incorporates a bidirectional I2C interface adjustment, mode SW , an AGC circuit and external stereo input switches (2 systems).

XF26175-333

Abstract: irm9
Contextual Info: XFMRS DWN.: C H K .:J L Ü _ APP.: J Ng DATF: Sep-30-04 DATF: Sep-30-04 DATF:5ep-30-04 XF26175 SERIES INDUCTORS M echanical D im ensions: S c h em atic: A 6.60 Max 0.260 Max 0.055 '1.40 a UNLESS OTHERWISE SPECIRED TOLERANCES: .xxx ±0.010 .xx ±0.25 I 0.160 I

P5506

Abstract: P5506BVG
Contextual Info: P5506BVG N-Channel Logic Level Enhancement NIKO-SEM SOP-8 Lead-Free Mode Field Effect Transistor D PRODUCT SUMMARY V BR DSS RDS(ON) ID 60 55mΩ 5.5A 4 :GATE 5,6,7,8 :DRAIN 1,2,3 :SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS

marking BCV

Abstract: bcv 49
Contextual Info: BCV 29, BCV 49 NPN Silicon Darlington Transistors 1 • For general AF applications 2 • High collector current 3 • High current gain • Complementary types: BCV 28, BCV 48 PNP 2 VPS05162 Type Marking Pin Configuration Package BCV 29 EF 1=B 2=C 3=E 4=C

BCV27

Abstract: BCP SOT23
Contextual Info: BCV 27, BCV 47 NPN Silicon Darlington Transistors 3 • For general AF applications • High collector current • High current gain • Complementary types: BCV 26, BCV 46 PNP 2 1 Type Marking Pin Configuration BCV 27 FFs 1=B 2=E 3=C SOT-23 BCV 47 FGs 1=B

Contextual Info: 74AC11245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS010B – JULY 1987 – REVISED APRIL 1996 D D D D D D DB, DW, NT, OR PW PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

AN5829S

Abstract: DBX V2 VCA
Contextual Info: ICs for TV AN5829S Sound multiplex decoder IC for the U.S. televisions • Overview 3 4 5 6 12 13 0.3 7.2±0.3 9.4±0.3 0.15 0.925 10 11 19 18 17 16 15 14 15.3±0.3 7 8 9 24 23 22 21 20 2.0±0.2 0.4±0.25 0.45 • Stereo demodulation, SAP demodulation, dbx noise reduction, AGC, external stereo input SW and I2C bus

Contextual Info: CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 D D D D D D Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM Applications Distributes One Differential Clock Input to Ten Differential Outputs

Contextual Info: 74AC11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS499A – DECEMBER 1986 – REVISED APRIL 1996 D D D D D, N, OR PW PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted

Contextual Info: CDCV857B 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS676 – JUNE 2002 D Phase-Lock Loop Clock Driver for Double D D D D D description GND Y0 Y0 VDDQ Y1 Y1 GND GND Y2 Y2 VDDQ VDDQ CLK CLK VDDQ AVDD AGND GND Y3 Y3 VDDQ Y4 Y4 GND 1 48 2 47 3 46 4 45 5 44 6 43 7 42

TI BINARY DATE CODE

Abstract: cd4028be CD4028BP ON cd4028
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS033A – Revised March 2002 The CD4028B-Series types are supplied in 16-lead hermetic dual-in-line ceramic packages D and F suffixes , 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (NSR suffix), and in chip

AN5819K

Abstract: dbx v1 ue26 AN581
Contextual Info: ICs for TV AN5819K Sound multiplex demodulator IC for TV in the North American market • Overview 28 27 26 25 24 23 22 21 20 19 18 17 16 15 • Stereo demodulation, SAP demodulation and dbx noise reduction are integrated into a single chip • Enabling various kinds of adjustment and mode

Contextual Info: SECURITIES AND EXCHANGE COMMISSION WASHINGTON, D.C. 20549 FORM 10-Q [X ] QUARTERLY REPORT PURSUANT TO SECTION 13 OR 15 d OF THE SECURITIES EXCHANGE ACT OF 1934 For the quarterly period ended March 31, 1999 [ ] TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE

Contextual Info: SECURITIES AND EXCHANGE COMMISSION WASHINGTON, D.C. 20549 FORM 10-Q [X ] QUARTERLY REPORT PURSUANT TO SECTION 13 OR 15 d OF THE SECURITIES EXCHANGE ACT OF 1934 For the quarterly period ended December 31, 1998 [ ] TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE

AN5849S

Abstract: SAP 17 dbx v1 DBX V2 VCA stereo multiplex decoder dbx noise reduction 723 ic block diagram DBX 202
Contextual Info: r Undement p lo e dev Multiplex Sound Demodulator IC AN5849S • Overview 5 6 10 11 19 18 17 16 15 14 12 13 0.15 0.925 0.3 7.2±0.3 9.4±0.3 ■ Applications 15.3±0.3 3 4 2.0±0.2 7 8 9 24 23 22 21 20 0.1±0.1 ● The adjustments of VCO and filter are free.

P2503BDG

Abstract: P2503BD nikos EQUIVALENT* P2503 P2503 niko-sem
Contextual Info: NIKO-SEM P2503BDG N-Channel Logic Level Enhancement Mode Field Effect Transistor TO-252 Lead-Free D PRODUCT SUMMARY V BR DSS RDS(ON) ID 30 25mΩ 12A 1.GATE 2.DRAIN 3.SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS

DHs SOT-23

Abstract: DFs SOT-23 sep 67a BCW67 das sot 23 67A SOT 23 6
Contextual Info: BCW 67, BCW 68 PNP Silicon AF Transistors 3 • For general AF applications • High current gain • Low collector-emitter saturation voltage • Complementary types: BCW 65, BCW 66 NPN 2 1 Type Marking Pin Configuration BCW 67A DAs 1=B 2=E 3=C SOT-23 BCW 67B

P2804

Abstract: P2804BVG
Contextual Info: P2804BVG N-Channel Logic Level Enhancement NIKO-SEM SOP-8 Lead-Free Mode Field Effect Transistor D 4 :GATE 5,6,7,8 :DRAIN 1,2,3 :SOURCE PRODUCT SUMMARY V BR DSS RDS(ON) ID 40V 28mΩ 7.5A G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise PARAMETERS/TEST CONDITIONS

Contextual Info: 74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 D D D D D D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB