SCLA007 Search Results

4000 series CMOS Logic ICs

Abstract: SCLA007A 74HC04 fan out sn74 series TTL logic gates list HC4040 application note schematic thyristor based inverter 74hc family Difference between LS, HC, HCT devices HC165 cmos 4000
Contextual Info: HCMOS Design Considerations SCLA007A September 2002 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services

4000 series CMOS Logic ICs

Abstract: sn74 series TTL logic gates list 74SC00 HC4000 cmos logic 4000 series Difference between LS, HC, HCT devices cmos 74C00 NAND DATA BOOK CD 4000 FAMILY 74hc family 40H00
Contextual Info: HCMOS Design Considerations SCLA007 April 1996 1 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest

Contextual Info: SN54HC374, SN74HC374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS141C – DECEMBER 1982 – REVISED JULY 1998 D D D D SN54HC374 . . . J OR W PACKAGE SN74HC374 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Eight D-Type Flip-Flops in a Single Package

SNJ54HC373FK

Contextual Info: SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B – DECEMBER 1982 – REVISED MAY 1997 D D D D Eight High-Current Latches in a Single Package High-Current 3-State True Outputs Can Drive up to 15 LSTTL Loads Full Parallel Access for Loading

Contextual Info: SN54HC02, SN74HC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS076B – DECEMBER 1982 – REVISED MAY 1997 D SN54HC02 . . . J OR W PACKAGE SN74HC02 . . . D, DB, N, OR PW PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D), Shrink Small-Outline

Contextual Info: SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148C – DECEMBER 1982 – REVISED JANUARY 1998 D D SN54HC574 . . . J OR W PACKAGE SN74HC574 . . . DW, N, OR PW PACKAGE TOP VIEW High-Current 3-State Noninverting Outputs

Contextual Info: SN54HC193, SN74HC193 4-BIT SYNCHRONOUS UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR SCLS122B – DECEMBER 1982 – REVISED MAY 1997 D D D D D Look-Ahead Circuitry Enhances Cascaded Counters Fully Synchronous in Count Modes Parallel Asynchronous Load for Modulo-N

Contextual Info: SN54HCT245, SN74HCT245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS020C – MARCH 1984 – REVISED MAY 1997 D D D SN54HCT245 . . . J OR W PACKAGE SN74HCT245 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible High-Current 3-State Outputs Drive Bus

Contextual Info: SN54HCT374, SN74HCT374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS005B – MARCH 1984 – REVISED MAY 1997 D D D D D SN54HCT374 . . . J OR W PACKAGE SN74HCT374 . . . DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Eight D-Type Flip-Flops in a Single Package

Contextual Info: SN54HCT240, SN74HCT240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS174C – MARCH 1984 – REVISED FEBRUARY 2000 D D SN54HCT240 . . . J OR W PACKAGE SN74HCT240 . . . DW, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer

pinout diagram of 4049

Contextual Info: [ /Title CD74H C4049, CD74H C4050 /Subject (High Speed CMOS Logic Hex CD54/74HC4049, CD54/74HC4050 Data sheet acquired from Harris Semiconductor SCHS205B High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting February 1998 - Revised May 2000 Features

Contextual Info: SN54HC08, SN74HC08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCLS081B – DECEMBER 1982 – REVISED MAY 1997 D SN54HC08 . . . J OR W PACKAGE SN74HC08 . . . D, N, OR PW PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W)

Contextual Info: SN54HC393, SN74HC393 DUAL 4-BIT BINARY COUNTERS SCLS143B – DECEMBER 1982 – REVISED MAY 1997 D D D D Dual 4-Bit Binary Counters With Individual Clocks Direct Clear for Each 4-Bit Counter Can Significantly Improve System Densities by Reducing Counter Package

Contextual Info: SN54HCT257, SN74HCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SCLS072B – NOVEMBER 1988 – REVISED MAY 1997 D D D D D SN54HCT257 . . . J PACKAGE SN74HCT257 . . . N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible

Contextual Info: SN54HC20, SN74HC20 DUAL 4-INPUT POSITIVE-NAND GATES SCLS086D – DECEMBER 1982 – REVISED FEBRUARY 2000 D SN54HC20 . . . J OR W PACKAGE SN74HC20 . . . D, DB, N, OR PW PACKAGE TOP VIEW Package Options Include Plastic Small-Outline (D), Shrink Small-Outline

Contextual Info: SN54HC165, SN74HC165 8-BIT PARALLEL-LOAD SHIFT REGISTERS SCLS116C – DECEMBER 1982 – REVISED MAY 1997 D D D D D Complementary Outputs Direct Overriding Load Data Inputs Gated Clock Inputs Parallel-to-Serial Data Conversion Package Options Include Plastic

Contextual Info: SN54HC273, SN74HC273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS136B – DECEMBER 1982 – REVISED MAY 1997 D D D D Contain Eight Flip-Flops With Single-Rail Outputs Direct Clear Input Individual Data Input to Each Flip-Flop Applications Include: – Buffer/Storage Registers

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS277 This data sheet is applicable to the CD54HC354 and CD74HCT356. The CD54HCT354, CD54HCT356, CD74HC356, and CD54HCT356 were not acquired from Harris Semiconductor. See SCHS179 for information on the CD74HC354 and CD74HCT354.

IC 74HC112

Abstract: 74HC112
Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141A Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised May 2000

Contextual Info: SN54HCT138, SN74HCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS171C – MARCH 1984 – REVISED MAY 1997 D SN54HCT138 . . . J OR W PACKAGE SN74HCT138 . . . D, N, OR PW PACKAGE TOP VIEW A B C G2A G2B G1 Y7 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC

74HC109

Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features

Contextual Info: SN54HCT244, SN74HCT244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS175B – MARCH 1984 – REVISED MAY 1997 D D SN54HCT244 . . . J OR W PACKAGE SN74HCT244 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer

SNJ54HC365

Contextual Info: SN54HC365, SN74HC365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS308B – JANUARY 1996 – REVISED MAY 1997 D D D SN54HC365 . . . J OR W PACKAGE SN74HC365 . . . D OR N PACKAGE TOP VIEW High-Current 3-State Outputs Drive Bus Lines, Buffer Memory Address Registers,

Contextual Info: SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325C – MARCH 1996 – REVISED SEPTEMBER 2000 D D D D D D D, DB, N, OR PW PACKAGE TOP VIEW High Degree of Linearity High On-Off Output Voltage Ratio Low Crosstalk Between Switches Low On-State Impedance . . . 50-Ω TYP