SBUS Search Results

STP4020

Contextual Info: S un M icroelectronics July 1997 PCMCIA Controller Interface DATASHEET D e s c r ip t io n The STP4020 PCMCIA controller bridges the SBus standard in SPARC microprocessor-based systems, to the PCMCIA Card Standard Interface. PCMCIA compatible peripheral cards provide a standard interface and

Contextual Info: STP2021 S un M ic r o e l e c t r o n ic s J u ly 1997 PMC Power Management Controller DATA SHEET D e s c r ip t io n The STP2021 Power Management Controller brings power management to SBus-based systems. The STP2021 interfaces to the SBus via the byte-wide expansion bus EBus provided by the STP2001 Slave I/O Controller.

STP2012

Abstract: SuperSPARC STP2016QFP
Contextual Info: STP2016 S un M ic r o e l e c t r o n ic s J u ly 1997 Clock-2 Generator DATA SHEET System Clock Generator D e s c r ip t io n The STP2016 Clock-2 Chip generates clock signals for components on the SBus and MBus. The MBus and SBus are used by SPARC processors, such as SuperSPARC™. The MBus is designed for multiprocessing MP , operating at

82077

Abstract: floppy controller 44 pin
Contextual Info: S un M icro electro nics July 1997 Slave I/O DATA SHEET Integrated SBus Interface Slave I/O Controller D e s c r ip t io n The STP2001Slave I/O Controller is a highly integrated, low-cost, low-power device designed for use in sin­ gle-processor systems with an SBus interface. The STP2001 provides serial I/O for keyboard, mouse and

PA15

Abstract: PA19 STP2001 STP2200ABGA STP2210QFP STP2220ABGA STP2230SOP
Contextual Info: Preliminary STP2220ABGA July 1997 U2S UPA-to-SBus Interface DATA SHEET DESCRIPTION The STP2220ABGA U2S [1] device bridges UPA- UltraSPARC Port Architecture to the SBus. U2S, is the primary connection between the UPA port (including UltraSPARC-I processors and memory) and the SBus

Merlin Gerin

Abstract: suconet 2761839 GERIN Phoenix contact subcon 9 connector saia
Contextual Info: Extract from the online catalog SUBCON-PLUS M2 Order No.: 2761839 D-SUB connector, 9-pin, with two cable entries, bus system: CAN, SUCONET K1, K2 MOELLER , SBUS (Saia), J-BUS (Merlin Gerin),

STP3010

Abstract: SUN HOLD ras 0910 ras 0910 STP3010PGA display duplo 27C256 MARK 4C7 BT467
Contextual Info: STP3010 July 1997 TGX DATA SHEET TurboGX Graphics Accelerator DESCRIPTION The STP3010 employs over 128,000 gates and implements an extended superset of previous GX architectures. This chip provides an integral SBus interface, VRAM video random-access memory controller, a high-performance math engine, plus a high-performance rendering (or drawing) engine. A complete graphics

sbus

Contextual Info: This is an abbreviated datasheet. Contact a Cypress representative for complete specifications. PY PPFdc; MBus to SBus Interface Controller • MBus to SBus Interface 32-bit slice • Allows MBus byte, halfword, word, and doubleword transactions • Allows SBus byte, halfword, and word

st24c02 eeprom circuit diagram

Abstract: programmation eprom ST24C02 alternate SDA st9 technical AN411 AN415 ST24C16 st25cxx ecron
Contextual Info: APPLICATION NOTE  USING THE I2C-bus PROTOCOL WITH THE ST9 Myriam Chabaud and Alan Dunworth INTRODUCTION The Serial Peripheral Interface SPI in the ST9 has been designed to handle a wide variety of serial bus protocols, including SBUS, IMBUS, and I2C-bus. Certain standard I2C-bus features have not been directly

Contextual Info: STP4020QFP S un M ic r o e l e c t r o n ic s J u ly 1997 PCMCIA Controller Interface DATA SHEET D e s c r ip t io n The STP4020 PCM CIA controller bridges the SBus standard in SPARC m icroprocessor-based systems, to the PCM CIA Card Standard Interface. PCM CIA com patible peripheral cards provide a standard interface and

Contextual Info: Preliminary STP2220ABGA S un M ic r o e l e c t r o n ic s J u ly 1997 U2S UPA-to-SBus Interface DATA SHEET D e s c r ip t io n The STP2220ABGA U2S ^ device bridges UPA- UltraSPARC Port Architecture to the SBus. U2S, is the prim ary connection betw een the UPA port (including UltraSPARC-1 processors and m em ory) and the SBus

Contextual Info: STP2012QFP S un M ic r o e l e c t r o n ic s J u ly 1997 DMA2 DATA SHEET SBus DMA Controller D e s c r ip t io n The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DM A access to one AM D Am 7990 Local Area N etw ork Control­

Contextual Info: STP2024 S un M ic r o e l e c t r o n ic s J u ly 1997 APC System Logic Chip DATA SHEET D e s c r ip t io n The STP2024 System Logic Chip provides additional features for SBus based systems. It has two m ajor logic blocks: an audio DM A controller and a glue logic block. The DM A controller consum es the bulk of the logic,

STP4020PQFP

Abstract: 80507 PCMCIA Controller
Contextual Info: STP4020QFP July 1997 PCMCIA Controller Interface DATA SHEET DESCRIPTION The STP4020 PCMCIA controller bridges the SBus standard in SPARC microprocessor-based systems, to the PCMCIA Card Standard Interface. PCMCIA compatible peripheral cards provide a standard interface and form factor for mass

Contextual Info: Preliminary Data Sheet October 1992 . -» A ra r M il# Microelectronics T7259 SBus Dual Basic Rate ISDN DBRI Transceiver Features • Simultaneous operation as both an ISON terminal endpoint (TE) and network termination (NT) — Supports CCITT 1.430/ANSI T1.605

L64853

Abstract: Emulex scsi processor Emulex dma controller chip
Contextual Info: L S I 45E D LO GI C CORP 53 0 4 6 0 4 Q 0 0 b 3 2 7 5 * L L C L T -5 Z -3 3 -M L64853 SBus DMA C ontroller Technical Manual I • I p.! i' ■M • • • •' %\ r 'V ' $ a v .i • • • • L S I 42E LOGI C CORP D ■ 53D46Q4 □□□b32fl 7 ■ LLC

TI16L8-15

Abstract: ti16l8 CMD27 TI16L815 1301P SBD21 TI16L8-1 SBD15 ti16l8- D1143
Contextual Info: Revision A TEXAS INSTRUMENTS Semiconductor Group TNETA1560/TNETA1500 Sbus Reference Schematic Notebook Physical Interface SONET 155 Mbps, Mutimode fiber Connector Revision A July 12, 1995 Questions may be directed to: TNETA TECHNICAL SUPPORT LINE *4ATM@ti.com

Contextual Info: Chapter 5 Bus Operations The TurboSPARC microprocessor contains four bus controllers along with four dedicated bus interfaces. 1. Secondary cache bus interface and controller 2. Main memory DRAM bus interface and controller 3. SBus interface and controller

Contextual Info: This is an abbreviated datasheet. Contact a Cypress representative for complete specifications. CYPRESS SEMICONDUCTOR Features • Supports two independent peripheral channels • Supports packing and unpacking from 32-bit SBus to 16- or 8-bit data paths • Byte, halfword, and word transfers

AAL5 SAR

Abstract: VMA-200 indigo intel i960 RISC forerunner atm VME64 GIA-200 irix
Contextual Info: ATM FORE SYSTEMS ForeRunner Family of ATM Adapters For UNIX Systems Adapters For EISA, PCI, SBUS, MCA, GIO and VME Bus Architectures • Multimode Fiber and Category 5 UTP ■ Flexible Cell Processing Software Can be Upgraded to Support Evolving ATM and Rate Control

QLA2204F-CK

Abstract: QLA2200-CK QLA2200F-CK QLA2200L-CK QLA2202F-CK
Contextual Info: SANblade 2200 1Gb Fibre Channel Solutions: PCI, CompactPCI and SBus Host Bus Adapters • • • • • • • • SERIES The SANblade 2200 Series is based on QLogic’s award winning Fibre Channel architecture and is designed for performance in the Storage

L64811

Abstract: M14008 video frame buffer AM27C256-205JC L64853 L64801 L64S24 L64825
Contextual Info: LSI ILOGIC 53G4ÖC4 DDlllSfl 7 3 cì BBLLC L64825 SBus Video Frame Buffer Technical Manual E3 S304504 ODll'iS'J b7S EE3LLC This document is preliminary. As such, it contains data derived from func­ tional simulations and performance estimates. LSI Logic has not verified the

L64853

Abstract: Emulex 1012207 Emulex Corporation scsi Emulex Corporation D012P Emulex scsi processor l64853aqc L64853A ESP100
Contextual Info: LSI LOGIC L64853A E nhanced SBus DMA Controller Technical M anual S3 0 4 S 0 4 DD1 2 B7 S 33^ « L L C Second Edition Document Number M S71-000104-99 B This document applies to revision A of the L64853A Enhanced SBus DMA Controller and to all subsequent versions unless otherwise indicated in a sub­

Contextual Info: Catalog 889409 PRODUCTS FOR DESKTOP PCs Revised 6-98 Bussing Connectors SBus Connectors — Subminiature D .050 Series III AMPUMITE 96 Position Headers Product Facts: • Meets requirements of VME bussing pcb per SBus standards ■ Plug and receptacle header