QD05 Search Results

diode ba 204

Abstract: PFZ33A DTZ100A DTZ11 DTZ22 PFZ350 PFZ36A DTZ100 DTZ110 DTZ110A
Contextual Info: 5^017=12=^37 S G S-THOMSON : O T H O M S O N -C S F DIVISION SEMICONDUCTEURS • ■ - 59C 0267 3 7^ QD05b73 D T-7/'3-3 r d tIr v r 6V8/A i î n 'A " DTZ 440,A UNI - A N D BIDIRECTIONAL TRANSIENT VOLTAGE SUPPRESSORS DIODES D E PROTECTION U N I - E T BIDIRECTIONNELLES

kopin

Abstract: kopin 320 KCD-QD05-AA cyberdisplay cyberdisplay 320 kopin 300m AMLCD kopin 640 kopin amlcd cyberdisplay 300m
Contextual Info: CyberDisplay 300M LV Ultra-Compact Monochrome AMLCD Frameless Part No. KCD-QD05-AA 1 General Description 1.2 Key Specifications The CyberDisplay® 300M LV is a monochrome activematrix liquid crystal display AMLCD . The active array of 300 x 225 pixels is surrounded by opaque dummy

kopin

Abstract: kopin 320 cyberdisplay scanner block diagram cyberdisplay 320 KCD-QD kopin Mono kopin lcd analog monochrome tv signal cyberdisplay 300m
Contextual Info: CyberDisplay 300M LV Part Number: KCD-QD05-AA Frameless F E A T U R E S • 300 x 225 active resolution ■ 320 x 240 total resolution ■ 11 µm H x 11 µm (V) pixel pitch ■ Ultra-compact (0.16” diagonal) ■ Active pixel area (3.30 mm x 2.475 mm)

BC250A

Contextual Info: 4684955 I T T S E M I C ON DU CTOR S PNP TRANSISTORS 07 87D 02322 D 7*. DeT | 4 ^ 0 4 ^ 5 5 QD05352 7 | I I V/mA Volts max.V mA/mA max. nA C 0b fr at - Vce/ - Ic at —Vce at - I c/ - I b V MHz < -& "IcES -V c E s a t at -V Ce/ - I c max. pF V 10 10 10 B B

QD05

Contextual Info: MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA 3.3V/2.5V 1:15 PECL/LVCMOS Clock Fanout Buffer The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less than 200 ps the device

MP3306

Abstract: CA3306 MP3306A MP3306AJS
Contextual Info: MP3306A m CMOS 6-Bit High Speed Analog-to-Digital Converter Micro Power Systems FEATURES • • • • • • • • • • Sampling Rates from 0.1 to 25 MHz MSPS 1/4 LSB DNL from 0.001 to 15 MHz Interface to any Input Range between GND and VDD Pipeline Mode (Pin Compatible Upgrade of MP3306)

k117

Abstract: BTS 308 k117 GR smi 5502 RFP 350 90 TSO-C148 prca murata stm stt 128 GR-253-CORE PM5346
Contextual Info: PMC-Sierra, Inc. S ta n d a rd P ro d u c t PMC-950919 I I V I V — P M 5 3 4 8 S /U N I- D U A L ISSUE 4 SATURN USER NETWORK INTERFACE FEA TU R ES • Single chip dual ATM User-Network Interface operating at 155.52 and 51.84 Mbit/s. • Provides essential hardware and software compatibility with industry-standard

Contextual Info: Freescale Semiconductor, Inc. Order number: MPC9449 RevSHEET 2, 08/2004 DATA TECHNICAL DATA 3.3 V/2.5 V 1:15 PECL/LVCMOS 3.3 V/2.5 V 1:15 PECL/LVCMOS Clock Fanout Buffer Clock Fanout Buffer The MPC9449 is a 3.3 V or 2.5 V compatible, 1:15 clock fanout buffer

Contextual Info: P S ta n d a rd P r o d u c t PMC-951010 I [ y I # | £ PM C-Sierra, Inc. ISSUE 4 PM5362 TUPP-PLUS SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FEATURES • Configurable, multi-channel, payload processor for aligning SONET virtual tributaries VTs or SDH tributary units (TUs) in an STS-3 or STM-1 byte serial

GM71C17403b

Abstract: GM71C17403BJ GM71C17403
Contextual Info: @ LG Semicon. Co. LTD. Features Description The GM71C17403B/BL is the new generation dynamic RAM organized 4,194,304 words x 4 bit. GM71C17403B/BL has realized higher density, higher perform ance and various functions by utilizing advanced CMOS process technology. The

Contextual Info: 3.3 V/2.5 V 1:15 PECL/LVCMOS Clock Fanout Buffer NRND – Not Recommend for New Designs MPC9449 NRND DATASHEET The MPC9449 is a 3.3 V or 2.5 V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to

Contextual Info: '99.5.20 K p g g g D t a » Multi LDOs for Cellular-phone R5310L series • OUTLINE The R5310L Series are Multi LDO regulators for power management o f cellular phones. All o f regulators are low noise and extremely low quiescent current by CMOS process. Each o f these ICs consists o f eight LDOs, voltage detectors, battery

Contextual Info: Tem ic M 67205 MATRA MHS 8K x 9 CMOS Parallel FIFO Introduction The M672Q5 implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word

transistor motorola 236

Abstract: AN1091 MPC9449 MPC949
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V/2.5V 1:15 PECL/LVCMOS Clock Fanout Buffer The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less than 200 ps the device

MAX34405

Abstract: ds1347 JESD22-C101 DALLAS DS80C320 maxim integrated date Code
Contextual Info: 11/18/2011 PRODUCT RELIABILITY REPORT FOR DS1347 Maxim Integrated Products 4401 South Beltwood Parkway Dallas, TX 75244-3292 Prepared by: Don Lipps Manager, Reliability Engineering Maxim Integrated Products 4401 South Beltwood Pkwy. Dallas, TX 75244-3292 Email: don.lipps@maxim-ic.com

RTC64611A

Abstract: RTC-64611 RTC64613 RTC-64613 rtc64613a
Contextual Info: Real time clock module 8-bit REAL TIME CLOCK MODULE RTC-64611/64613 • • • • • • • • • Builtin crystal unit allows adjustment-free efficient operation. 8-bit data bus and high speed access 85 nsec. max. . Provided with the same interface as S-RAM and battery backup function.

ECG861

Abstract: ecg jfet
Contextual Info: P H IL I P S E C G INC 17E ECG • ^53=120 000S03Ô 1 ■ 7 '- ^ / - / / ECG861 Quad Single Pole Analog Sw Sem iconductors Features • Analog signals are not loaded • Constant "O N " resistance for signals up to ±10 V and 100 kHz • Sm all signal analog signals to 50 MHz

AN1091

Abstract: MPC9449 MPC949
Contextual Info: MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA 3.3V/2.5V 1:15 PECL/LVCMOS Clock Fanout Buffer The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less than 200 ps the device

Contextual Info: 3.3 V/2.5 V 1:15 PECL/LVCMOS Clock Fanout Buffer MPC9449 NRND DATASHEET NRND – Not Recommend for New Designs The MPC9449 is a 3.3 V or 2.5 V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to

Contextual Info: MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order Number: MPC9449/D Rev 1, 08/2002 DATA SHEET 3.3V/2.5V 1:15 PECL/LVCMOS Clock 3.3V/2.5V 1:15 PECL/LVCMOS Fanout Buffer Clock Fanout Buffer The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer

semi catalog

Abstract: j510 Motorola transistor smd marking codes rf choke cross comparison books TTL catalog IC Data-book MPC930 MPC9449 MPC951 MPC952
Contextual Info: Freescale Semiconductor Data Book. Advanced Clock Drivers. DL207 Rev. 2 8/2004 Advanced Clock Drivers Selector Guide 1 Clock Generator Data Sheets 2 QUICCClock Generator Data Sheets 3 Failover or Redundant Clock Data Sheets 4 Clock Synthesizer Data Sheets

EXC-ML32A68OU

Abstract: FB215 74LPT16244 XC9536XLVQ64 DIP-SW5 XC9536XL-VQ64 IO113 74LPT16374 RxC11 dipsw
Contextual Info: 5 4 3 2 1 D D ISL5216EVAL Schematics Table Of Contents Page 1 ISL5216EVAL Schematics - Title Page Page 2 ISL5216EVAL Schematics - ISL5216 Page 3 ISL5216EVAL Schematics - Data Input Page 4 ISL5216EVAL Schematics - Data Output Page 5 ISL5216EVAL Schematics - Clock Distribution

Contextual Info: AT43216 Features • One-Chip SCSI-2 Fast Architecture Controller for Host and 8-blt or 16-btt Peripheral Applications • 84-Pin PLCC Package, Sub-Micron CMOS Technology • Supports ANSI X3T9.2 SCSI Standard, with SCSI-2 Fast Architecture • Functions as an Initiator or a Target

Contextual Info: • A3623&3 Q0DS37L, TS1 « S O N Y SONY C X K 1 2 0 6 A M /A T M Video Signal Field Memory D escription The C X K 1 2 0 6 A M /A T M is a 3 -p o rt VRAM capable o f coping w ith both NTSC and PAL and o f storing pictures fo r one 8-bit field w ith tw o