PORT LATCH Search Results

ECP88

Contextual Info: PARALLEL PORT The FDC37C669 incorporates an IBM XT/AT compatible parallel port. The FDC37C669 supports the optional PS/2 type bi­ directional parallel port SPP , the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the

XTAL1

Abstract: pca816 addr alu circuit with transistor 0p07
Contextual Info: P0.0–P0.7 P2.0–P2.7 PORT 0 DRIVERS PORT 2 DRIVERS VCC VSS RAM ADDR REGISTER PORT 0 LATCH RAM PORT 2 LATCH FLASH 8 B REGISTER STACK POINTER ACC PROGRAM ADDRESS REGISTER TMP1 TMP2 BUFFER ALU SFRs TIMERS PSW PC INCREMENTER P.C.A. 8 16 PSEN ALE EAVPP TIMING

Hitachi PIX-8144

Abstract: Hitachi PIX 8144 Pix-8144 PIX 8144 hitachi 8144 CY7C025-AC dual port 16 SRAM PLCC CY7C024 CY7C0241 CY7C0251
Contextual Info: Qualification Report QTP 96091/96393, Version 2.0 September 1996 Dual Port SRAM - R28 Technology, 6% Shrink CY7C0251 8K x 18 Dual Port SRAM CY7C025 8K x 16 Dual Port SRAM CY7C0241 4K x 18 Dual Port SRAM CY7C024 4K x 16 Dual Port SRAM CY7C145 8K x 9 Dual Port SRAM

96182

Abstract: cy7c024 CY131 CY7C0241 CY7C133 CY7C1342 CY7C135 CY7C138 CY7C139 CY7C143
Contextual Info: Qualification Report September 1996, QTP# 96182/96354, Version 2.0 Dual Port SRAM - R28 Technology CY7C0241 4K x 18 Dual Port SRAM CY7C024 4K x 16 Dual Port SRAM CY7C145 8K x 9 Dual Port SRAM CY7C144 8K x 8 Dual Port SRAM CY7C139 4K x 9 Dual Port SRAM CY7C134

ADI1290

Abstract: DSP56001 MBD301 MC6800 MC68000
Contextual Info: SECTION 9 PORT A Port A is the memory expansion port that can be used for either memory expansion or for memory-mapped I/O see 2.9.1 Expansion Port (Port A . A number of features make port A versatile and easy to use. These features provide a low-parts-count connection

dual port SRAM PLCC

Abstract: CY7C133 CY7C138 CY7C139 CY7C143 CY7C144 CY7C145 CY7C016 CY7C024 CY7C0241
Contextual Info: Qualification Report May 1996, QTP# 95226, Version 1.0 Dual Port SRAM - R28 Technology Thin Quad Flat Pack Package CY7C0251 8K x 18 Dual Port SRAM CY7C025 8K x 16 Dual Port SRAM CY7C0241 4K x 18 Dual Port SRAM CY7C024 4K x 16 Dual Port SRAM CY7C145 8K x 9 Dual Port SRAM

Ablestik

Abstract: CY7C024 CY7C0241 CY7C139 CY7C144 CY7C145
Contextual Info: Cypress Semiconductor Qualification Report QTP# 98393 VERSION 1.3 March, 1999 Dual Port SRAM - R28 Technology - Fab 2 CY7C0241 4K x 18 Dual Port SRAM CY7C024 4K x 16 Dual Port SRAM CY7C145 8K x 9 Dual Port SRAM CY7C144 8K x 8 Dual Port SRAM CY7C139 4K x 9 Dual Port SRAM

intel 82360SL

Abstract: 82360SL B2091
Contextual Info: intel« 82091AA 6.0 PARALLEL PORT The 82091AA parallel port can be configured for four parallel port modes. These parallel port modes and the associated parallel interface protocols are: Parallel Port Mode Parallel Interface Protocol ISA-Compatible Mode Compatibility, Nibble

Contextual Info: TOSHIBA TM P90C840A/841 A 3.5.4 Port 3 P30~P37 Port 3 is an 8-bit general-purpose I/O port P3 with fixed I/O function. All bits of the output latch are initialized to “1” by resetting, and “High level” is generated to the output port. In addition to the I/O port function, P30~P34 have the I/O function for the internal

AL010

Abstract: AR11 AR12 CY7C132 CY7C142 DR31 "Single-Port RAM"
Contextual Info: Understanding Asynchronous Dual-Port RAMs This application note examines the evolution of multi-port memories and explains the operation and benefits of Cypress’s asynchronous dual-port RAMs. It also explores the benefits of using dual-port RAMs over single-port RAMs in

dual port ram

Abstract: AR11 AR12 CY7C132 CY7C142 DR31
Contextual Info: Understanding Asynchronous Dual-Port RAMs This application note examines the evolution of multi-port memories and explains the operation and benefits of Cypress’s asynchronous dual-port RAMs. It also explores the benefits of using dual-port RAMs over single-port RAMs in

Contextual Info: FAST CMOS OCTAL REGISTER TRANSCEIVER WITH PARITY Integrated Device Technology, Inc* FEATURES PRELIMINARY IDT73210/A/B IDT73211/A/B 73210/211 Single-level pipeline register from Port A to Port B 73210 Two level pipeline register from Port B to Port A 73211 Single level pipeline register from Port B to Port A

AD3b

Abstract: ad4a AD7B dual-port RAM DS1609 DS1609S AD5A 256 byte dual port memory
Contextual Info: DS1609 DS1609 Dual Port RAM FEATURES PIN ASSIGNMENT • Totally asynchronous 256 byte dual port memory PORT A PORT B AD7A 1 24 VCC AD6A 2 23 OEB AD5A 3 22 CEB port memory cell allows random access with minimum arbitration AD4A 4 21 WEB AD3A 5 20 AD0B • Each port has standard independent RAM control sig-

ADI1290

Abstract: rom 2716 DSP56001 users manual DSP56001 MBD301 MC6800 MC68000
Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. SECTION 9 PORT A Port A is the memory expansion port that can be used for either memory expansion or for memory-mapped I/O see 2.9.1 Expansion Port (Port A . A number of features make port A versatile and easy to use. These features provide a low-parts-count connection

transistor p35

Abstract: UM97Z8X0104 P2M TRANSISTOR AD08 transistor P32 25
Contextual Info: USER’S MANUAL 5 CHAPTER 5 I/O PORTS 5.1 I/O PORTS The Z8 has up to 32 lines dedicated to input and output. These lines are grouped into four 8-bit ports known as Port 0, Port 1, Port 2, and Port 3. Port 0 is nibble programmable as input, output, or address. Port 1 is byte configurable as

BC634

Abstract: AA012 DSP56800 bc645 BC699 bc657
Contextual Info: SECTION 12 JTAG PORT DSP56L811 User’s Manual 12-1 JTAG Port 12.1 12.2 12.3 12.4 12.5 12-2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 JTAG PORT ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . 12-4 JTAG/ONCE PORT PINOUT. . . . . . . . . . . . . . . . . . . . . . . . 12-5

CYPRESS CROSS REFERENCE dual port sram

Abstract: 1024 byte dual port memory "8-Bit Microprocessors" CY7C132 dual port sram dual port SRAM PLCC dual-port RAM AR11 AR12 CY7C142
Contextual Info: fax id: 5300 Understanding Asynchronous Dual-Port RAMs This application note examines the evolution of multi-port memories and explains the operation and benefits of Cypress’s asynchronous dual-port RAMs. It also explores the benefits of using dual-port RAMs over single-port RAMs in

D42264

Abstract: HPD42264C-10 JHPD42264 JJPD42264 JUPD42264 PPD42264 D4226
Contextual Info: NEC JVPD42264 Dual-Port Graphics Buffer N EC E lec tro n ics Inc. Description Features The ¿iPD42264 is a dual-port graphics buffer equipped with a 64K x 4-bit random access port and a 256 x 4-bit serial read port. The serial read port is connected to an

Contextual Info: TOSHIBA TMP90C840A/841A 3.5.5 P o rt4 P 40~ P 4 3 Port 4 is a 4-bit port P4 intended only for the output. All bits of the output latch are initialized to “0” by resetting, and “0” is generated to the port. In addition to the output port function, it works as an address bus (A16~A19). The

hpc46900

Abstract: uPI Semiconductor package h8c
Contextual Info: PRELIM INARY HPC16900/HPC26900/HPC36900/HPC46900 PEARL Port Expander And Re-creation Logic G eneral Description The PEARL is a peripheral device which re-creates Port A and four bits of Port B when used with HPC family microcon­ trollers. An additional 16-bit port Port PC is configured as

96182

Abstract: 9715 cy7c136
Contextual Info: Cypress Semiconductor Qualification Report QTP# 97045/97154 VERSION 1.1 April, 1997 Dual Port SRAM - R28 Technology CY7C130/131 1K x 8 Dual Port SRAM CY7C140/141 1K x 8 Dual Port SRAM CY7C132/136 2K x 8 Dual Port SRAM CY7C142/146 2K x 8 Dual Port SRAM Cypress Semiconductor

Contextual Info: VLSI Technology , in c . ADVANCE INFORMATION BUSY FLAGS VT71321 • VT71421 _ LOW until the right port reads data from the same location. Similarly, if the right port writes to memory location 7FE HEX , the left port Interrupt flag (INTL) is latched LOW

CYD18S18V18-200BBAXI

Abstract: FullFlex36 CYD36S18V18-167BGXI
Contextual Info: FullFlex FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with single data rate SDR operation on each port

upd42274

Abstract: PD42274-80 JPD42274 PD4227
Contextual Info: NEC pPD42274-80 Dual-Port Graphics Buffer NEC Electronics Inc. Description Features The pPD42274-80 is a dual-port graphics buffer equipped with a 256Kx 4-bit random access port and a 512 x 4-bit serial read port. The serial read port is connected to an internal 2048-bit data register through