CY7C139 Search Results

016v

Contextual Info: fax id: 5212 51 CY7C138V/144V/006V/007V PRELIMINARY CY7C139V/145V/016V/017V 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Features • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device

Contextual Info: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth

9l reset

Contextual Info: 51 CY7C138V/144V/006V/007V PRELIMINARY CY7C139V/145V/016V/017V 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device • On-chip arbitration logic

1709 013

Abstract: CY7C1399BN CY7C1399BN-12VC CY7C1399BN-12VXC CY7C1399BN-12VXI CY7C1399BN-12ZC CY7C1399BN-12ZXC CY7C1399BNL-12ZC CY7C1399BNL-12ZXC
Contextual Info: CY7C1399BN 256K 32K x 8 Static RAM Features expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tri-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected.

Contextual Info: 399 CY7C1399 32K x 8 3.3V Static RAM Features • Single 3.3V power supply • Ideal for low-voltage cache memory applications • High speed — 12/15 ns • Low active power — 255 mW max. • Low CMOS standby power (L) — 180 µW (max.), f=fMAX • 2.0V data retention (L)

Contextual Info: CY7C1393BV18 CY7C1394BV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture Features Functional Description • 18 Mbit density 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces

Contextual Info: CY7C1392BV18 CY7C1992BV18 CY7C1393BV18 CY7C1394BV18 18-Mbit DDR-II SIO SRAM 2-Word Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency

Contextual Info: 399B CY7C1399B 32K x 8 3.3V Static RAM Features pansion is provided by an active LOW Chip Enable CE and active LOW Output Enable (OE) and three-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected.

CYPRESS CROSS REFERENCE dual port sram

Abstract: CY7C006AV CY7C007AV CY7C016AV CY7C017AV CY7C138AV CY7C139AV CY7C144AV CY7C145AV
Contextual Info: CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3 V 8 K / 16 K x 8 Dual-Port Static RAM CY7C144AV CY7C006AV 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous

SEM 2005 16 PINS

Abstract: pin diagram of sem 2005 CY7C138 CY7C139 sem 2005 16 pin 25j81
Contextual Info: CY7C138 CY7C1394K x 8/9 Dual-Port Static RAM with Sem, Int, Busy CY7C138 CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features • True Dual-Ported memory cells that allow simultaneous reads of the same memory location • 4K x 8 organization CY7C138

Contextual Info: 1 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV PRELIMINARY 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 4K/8K/16K/32K x 8 organizations CY7C0138AV/144AV/

Contextual Info: CY7C1399BN 256 K 32 K x 8 Static RAM Functional Description Features The CY7C1399BN is a high-performance 3.3 V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tristate drivers. The

CY7C1399B

Abstract: CY7C1399B-12VC CY7C1399B-15VXC
Contextual Info: CY7C1399B 256K 32K x 8 Static RAM Features active LOW Output Enable (OE) and three-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. • Single 3.3V power supply • Ideal for low-voltage cache memory applications

577w

Abstract: CY7C1399V A6213
Contextual Info: CY7C1399V 32K x 8 3.0V Static RAM Features D D Single 3.0V The CY7C1399V is a highĆperformance 3.0V CMOS static RAM organized as 32,768 words by 8 bits. Easy memory exĆ pansion is provided by an active LOW chip enable CE and active LOW output enĆ able (OE) and threeĆstate drivers. The deĆ

Contextual Info: CY7C1393CV18 CY7C1394CV18 18-Mbit DDR II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit Density 1M x 18, 512K x 36 ■ 300 MHz Clock for high Bandwidth ■ 2-word Burst for reducing Address Bus Frequency ■ Double Data Rate (DDR) Interfaces

CY7C1399

Abstract: EME-6300H
Contextual Info: Qualification Report July 1996, QTP# 95417, Version 2.0 CY7C1399 32K x 8, 3.3V Static RAM PRODUCT DESCRIPTION (for qualification) Information provided in this document is intended for generic qualification and technically describes the Cypress part supplied:

CY7C1395V25

Contextual Info: 395 CY7C1395 CY7C1395V25 PRELIMINARY 2M x36 PBSRAM with NoBL -Burst Architecture Features to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1395V25 operates with a 2.5V power supply and the CY7C1395 operates

70V06

Abstract: IDT70V05
Contextual Info: 1 CY7C138V/144V/006V/007V PRELIMINARY CY7C139V/145V/016V/017V 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM • Fully asynchronous operation • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device

CY7C1392V18

Abstract: CY7C1393V18 CY7C1394V18
Contextual Info: 392V18 CY7C1392V18 CY7C1393V18 CY7C1394V18 ADVANCE INFORMATION 18-Mb SRAM with DDR-II SIO Architecture Features Functional Description • 18-Mb Density 2M x 8, 1M x 18, 512K x 36 — Supports concurrent transactions • 300-MHz Clock for High Bandwidth

Contextual Info: 7c1399: Monday, November 16,1992 Revision: Wednesday, January 6,1993 CY7C1399 ADVANCED INFORMATION CYPRESS t SEMICONDUCTOR = ' 3.3V 32Kx 8 Static RAM • Automatic power-down when deselected Features • Single 3 3 ± 0.3V power supply • H ighspeed — 15 ns

68LEAD

Contextual Info: CY7C138, CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features Functional Description • True Dual-Ported memory cells that enable simultaneous reads of the same memory location ■ 4K x 8 organization CY7C138 ■ 4K x 9 organization (CY7C139)

Contextual Info: CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency

CY7C1399BN

Abstract: CY7C1399BN-12VC CY7C1399BN-12VXC CY7C1399BN-12VXI CY7C1399BN-12ZC CY7C1399BN-12ZXC CY7C1399BNL-12ZC CY7C1399BNL-12ZXC
Contextual Info: CY7C1399BN 256K 32K x 8 Static RAM Features expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tri-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected.

Contextual Info: CY7C1393BV18 CY7C1394BV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture Features Functional Description • 18 Mbit density 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces