CY7C138 Search Results

CY7C1382DV33-200BZI

Contextual Info: CY7C1380DV33 CY7C1382DV33 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades is 200 MHz ■ Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1388 ADVANCED INFORMATION CYPRESS SEMICONDUCTOR Features • Single 3 3 ± 0.3V power supply • High speed — 20 ns • Low active power — 235 m W • Low standby power — 90 mW • 2.0V data retention — 100 iW • Ideal for low-voltage cache memory

CY7C1386C

Abstract: CY7C1387C
Contextual Info: CY7C1386C CY7C1387C 18-Mb 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

CY7C1381B-100AI

Abstract: 381B CY7C1381B CY7C1381B-117AC CY7C1383B
Contextual Info: 381B CY7C1381B CY7C1383B 512 x 36/1M × 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 10.0 ns Fast clock speed: 117, 100, 83 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion

CY7C1381A

Abstract: CY7C1381A-100AC CY7C1381A-117AC CY7C1381A-83AC
Contextual Info: CY7C1381A CY7C1383A PRELIMINARY 512K x 36 / 1M x 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 9.0, 10.0 ns Fast clock speed: 117, 100, 83, 66 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion

CY7C1380BV25

Abstract: CY7C1382BV25
Contextual Info: CY7C1380BV25 CY7C1380BV25 CY7C1382BV25 PRELIMINARY 512K x 36 / 1 Mb x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 200,166, 150, 133 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns

016v

Contextual Info: fax id: 5212 51 CY7C138V/144V/006V/007V PRELIMINARY CY7C139V/145V/016V/017V 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Features • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device

Contextual Info: CY7C1386D CY7C1387D 18-Mbit 512 K x 36/1 M × 18 Pipelined DCD Sync SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades are 200, and 167 MHz ■

9l reset

Contextual Info: 51 CY7C138V/144V/006V/007V PRELIMINARY CY7C139V/145V/016V/017V 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device • On-chip arbitration logic

Contextual Info: CY7C1381DV25 CY7C1383DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations • 512K x 36/1 Mbit x 18 common I/O • 2.5V –5% and +10% core power supply (VDD) • 2.5V I/O supply (VDDQ)

1382C

Contextual Info: 380C CY7C1380C CY7C1382C PRELIMINARY 512K x 36 / 1M x 18 Pipelined SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 250, 225, 200, 167 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns

CY7C1381c-100ac

Contextual Info: 381C CY7C1381C CY7C1383C PRELIMINARY 512K x 36/1M x 18 Flow-Thru SRAM Features • • • • • • • • • • • • Fast access times: 6.5, 7.5, 8.5 ns Fast clock speed: 133, 117, 100 MHz Provide high-performance 2-1-1-1 access rate Optimal for depth expansion

Contextual Info: CY7C1380D CY7C1382D PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM 18-Mbit (512 K × 36/1 M × 18) Flow Through SRAM Features Functional Description • Supports 133 MHz bus operations ■ 512 K × 36 and 1 M × 18 common I/O ■ 3.3 V core power supply (VDD)

Contextual Info: CY7C1381DV25 CY7C1383DV25 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM Functional Description[1] Features • Supports 133-MHz bus operations • 512K x 36/1M x 18 common I/O • 2.5V core power supply (VDD) • 2.5V I/O supply (VDDQ) • Fast clock-to-output times

CYPRESS CROSS REFERENCE dual port sram

Abstract: CY7C006AV CY7C007AV CY7C016AV CY7C017AV CY7C138AV CY7C139AV CY7C144AV CY7C145AV
Contextual Info: CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3 V 8 K / 16 K x 8 Dual-Port Static RAM CY7C144AV CY7C006AV 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM 3.3 V 8 K / 16 K × 8 Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous

CY7C1380DV25

Abstract: CY7C1382DV25
Contextual Info: CY7C1380DV25 CY7C1382DV25 PRELIMINARY 18-Mbit 512K x 36/1M x 18 Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

CY7C1386CV25

Abstract: CY7C1387CV25
Contextual Info: CY7C1386CV25 CY7C1387CV25 18-Mb 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200 and 167 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: CY7C1381D CY7C1383D CY7C1383F 18-Mbit 512 K x 36/1 M × 18 Flow-Through SRAM 18-Mbit (512 K × 36/1 M × 18) Flow Through SRAM Features Functional Description • Supports 133 MHz bus operations ■ 512 K × 36 and 1 M × 18 common I/O ■ 3.3 V core power supply (VDD)

SEM 2005 16 PINS

Abstract: pin diagram of sem 2005 CY7C138 CY7C139 sem 2005 16 pin 25j81
Contextual Info: CY7C138 CY7C1394K x 8/9 Dual-Port Static RAM with Sem, Int, Busy CY7C138 CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features • True Dual-Ported memory cells that allow simultaneous reads of the same memory location • 4K x 8 organization CY7C138

Contextual Info: 1 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV PRELIMINARY 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 4K/8K/16K/32K x 8 organizations CY7C0138AV/144AV/

Contextual Info: fax id: 5204 C Y 7 C 1 3 8 C Y 7 C 1 3 9 CYPRESS 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features are included on the CY7C138/9 to handle situations when mul­ tiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for

A011 transistor

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 38-06037 Spec Title: CY7C138 4K X 8/9 DUAL-PORT STATIC RAM WITH SEM , INT, BUSY Sunset Owner: Adithi Perepu Replaced by: NONE CY7C138 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features Functional Description • True dual-ported memory cells that enable simultaneous reads

Contextual Info: CY7C1380D CY7C1380F CY7C1382D 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation