CY7C135 Search Results

CY7C1350

Abstract: IDT71V546 MCM63Z736
Contextual Info: fax id: 1103 CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V546, MT55L128L36P and MCM63Z736 • Supports 143-MHz bus operations with zero wait

7C1351-40

Abstract: 7C1351-50 7C1351-66 CY7C1351 IDT71V547 MCM63Z737
Contextual Info: fax id: 1102 CY7C1351 PRELIMINARY 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V547, MT55L128L36F and MCM63Z737 • Supports 66-MHz bus operations with zero wait states

CY7C1355C

Contextual Info: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead

Contextual Info: CY7C1352G 4-Mbit 256 K x 18 Pipelined SRAM with NoBL Architecture 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need

CY7C1352

Abstract: MCM63Z818 MCM63Z819
Contextual Info: CY7C1352 CY7C1352 256K x18 Pipelined SRAM with NoBL Architecture Features • Low standby power Functional Description • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z818 and MT55L256L18P • Supports 143-MHz bus operations with zero wait states

CY7C1352B-100AC

Abstract: cy7c1352b-166ac CY7C1352B MCM63Z818 MCM63Z819 1352B-2
Contextual Info: PRELIMINARY CY7C1352B 256K x18 Pipelined SRAM with NoBL Architecture • Low standby power Features Functional Description The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of

CY7C1354C

Abstract: CY7C1356C
Contextual Info: CY7C1354C CY7C1356C 9-Mbit 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200, and 166 MHz

GVT71256ZC36B-7.5

Abstract: CY7C1356A-100AC CY7C1356A GVT71512ZC18
Contextual Info: PRELIMINARY CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256Kx36/512Kx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 200, 166, 133, and 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns

CY7C1357A

Abstract: GVT71512ZB18
Contextual Info: CY7C1357A PRELIMINARY CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 133, 117, and 100 MHz • Fast access time: 6.5, 7.0, 7.5, and 8.0 ns

CY7C1350

Contextual Info: fax id: 1103 * g S S M ^ % rrv rt n n n CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture F e a tu re s F u n c t io n a l D e s c r ip t io n • Pin compatible and functionally e q u iv a le n ts ZBT™ devices IDT71V546, MT55L128L36P and MCM63Z736

7C1351-40

Abstract: 7C1351-50 7C1351-66 CY7C1351 IDT71V547 MCM63Z737 DQ31-0
Contextual Info: fax id: 1102 Back CY7C1351 PRELIMINARY 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V547, MT55L128L36F and MCM63Z737 • Supports 66-MHz bus operations with zero wait states

CY7C1352

Abstract: MCM63Z818 MCM63Z819
Contextual Info: fax id: 1101 Back CY7C1352 PRELIMINARY 256K x18 Pipelined SRAM with NoBL Architecture Features • Low standby power • Pin compatible and functionally equivalent to ZBT devices MCM63Z818 and MT55L256L18P • Supports 143-MHz bus operations with zero wait states

CY7C1342

Abstract: CY7C135
Contextual Info: 342 and 4K x 8 Dual-Port Static RAM with Semaphores CY7C135 CY7C1342 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Features • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 4K x 8 organization

EOIZ

Contextual Info: CY7C1351 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description The CY7C1351 is a 3.3V 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the

CY7C1352

Abstract: MCM63Z818 MCM63Z819
Contextual Info: PRELIMINARY CY7C1352 256K x18 Pipelined SRAM with NoBL Architecture • Low standby power Features • Pin compatible and functionally equivalent to ZBT devices MCM63Z818 and MT55L256L18P • Supports 143-MHz bus operations with zero wait states — Data is transferred on every clock

CY7C1352G

Abstract: CY7C1352G-166AXC CY7C1352G-166AXI CY7C1352G-200AXC CY7C1352G-200AXI CY7C1352G-250AXC CY7C1352G-250AXI
Contextual Info: CY7C1352G PRELIMINARY 4-Mbit 256Kx18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE

cy7c1354c-200bgxc

Abstract: CY7C1354C CY7C1356C M11 68
Contextual Info: CY7C1354C CY7C1356C 9-Mbit 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200, and 166 MHz

4435a

Abstract: CY7C1353G CY7C1353G-133AXC
Contextual Info: CY7C1353G 4-Mbit 256K x 18 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Supports up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices

7C1354V25-100

Abstract: CY7C1354 CY7C1354V25 CY7C1356V25 R1538
Contextual Info: 356V25 CY7C1354V25 CY7C1356V25 PRELIMINARY 256Kx36/512Kx18 Pipelined SRAM with NoBL Architecture Features • Pin compatible and functionally equivalent to ZBT™ • Supports 200-MHz bus operations with zero wait states — Data is transferred on every clock

sem 2005

Abstract: CY7C1342 CY7C135
Contextual Info: CY7C135 CY7C1342 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 4K x 8 organization • 0.65-micron CMOS for optimum speed/power

CY7C1354C-200BGXC

Contextual Info: CY7C1354C CY7C1356C 9-Mbit 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200, and 166 MHz

Contextual Info: CY7C1354CV25 CY7C1356CV25 9-Mbit 256 K x 36/512 K × 18 Pipelined SRAM with NoBL Architecture 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible with and functionally equivalent to ZBT™

Contextual Info: CY7C1351G 4-Mbit 128K x 36 Flow-through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™

CY7C1350B-80AC

Abstract: CY7C1350B
Contextual Info: PRELIMINARY CY7C1350B 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices IDT71V546, MT55L128L36P, and MCM63Z736 • Supports 166-MHz bus operations with zero wait states