MSL260G
Abstract: MSL-260-G D0806 R0807 T0803 D0802 D0807 RDD0804 D0808 5 pin reset ic ARB
Contextual Info: Using the Intel 80960 CA with the PCI 9060 PCI evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000 0-15 Vendor ID, Allocated to PLX by PCI SIG (Read-only) (Default = 10B5)
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pci90600x000000000x000000020x00000004+15100ns200ns300ns80960capclk1-33msl260gmsl-260-gd0806r0807t0803d0802d0807rdd0804d08085 pin reset ic arb
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UPD720101GJ-UEN
Abstract: UPD720101 34c72 787616-1 NEC AMC OSC48MHz AD27 AD29 AD30 NEC A61
Contextual Info: 4 3 5V 3.3V AD17 CBE20 C IRDY0 DEVSEL0 PERR0 SERR0 CBE10 AD14 AD12 AD10 AD8 AD7 AD5 AD3 AD1 AD18 AD16 FRAME0 TRDY0 STOP0 PAR AD15 AD13 AD11 3.3V 1 36 1% 2 1 R54 36 1% 2 1 RSDM4 DM4 DP4 RSDP4 132 133 135 136 R57 36 1% 2 1 R56 36 1% 2 1 RSDM5 DM5 DP5 RSDP5 138
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cbe20cbe10r67egulatorupc29l33t+14150ufblm21pg600sn1upd720101et-0143disg-2ue-00070upd720101gj-uen34c72787616-1nec amcosc48mhzad27ad29ad30nec a61
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la1 d22
Abstract: la2 d2 timer rn0805 U0301 L16 eeprom 80960CA LD11 LD12 U0101 PCI9060 68040
Contextual Info: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 6 |LINK |P2.SCH |P3.SCH |P4.SCH |P5.SCH |P6.SCH |P7.SCH |P8.SCH
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u0101pci906080960cau0102+1020v8rpci9060/68040la1 d22la2 d2 timerrn0805u0301l16 eepromld11ld12pci9060 68040
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Y0803
Abstract: U0801B IC LM7805 N1 Y10 pin diagram of IC LM7805 C0801 STI3400 U0101 U0604 plx9060
Contextual Info: Q CL 7 D PR 3 4 14 2 U?A Q 5 CLK 6 {Value} 1 1 2 3 4 5 6 SPARE GATES: 8 ECN HISTORY DESCRIPTION REV 2 -ADD CDREQ DATE APPROVAL 10/24/95 U0101 PU0101 A PU0102 PU0103 12 11 D U0801B 9 Q CLK 8 Q 74ACT74 13 20V8C DIP 22 21 20 19 18 17 16 15 CL O1 IO2 IO3 IO4 IO5
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u0101pu0101pu0102pu0103+12u0801b74act7420v8cpu0104y0803ic lm7805n1 y10pin diagram of ic lm7805c0801sti3400u0604plx9060
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mah8
Abstract: MDL22 u0502a LD11 LD12 U0101 RN05 RN0501 U0302
Contextual Info: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 6 |LINK |P2.SCH |P3.SCH |P4.SCH |P5.SCH |P6.SCH |P7.SCH 7
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u0101pci90609060/dramu0102+1020v8rpci9060/drammah8mdl22u0502ald11ld12rn05rn0501u0302
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L1239
Abstract: l0728 l0312 SGS L282 L0936 L11616 L9960 0x00000404 L1198 L1322
Contextual Info: Go to next Section: PCI to Local Bridge Performance Study Return to Table of Contents Using the PCI 9060 without a CPU SGS Thomson MPEG with PCI 9060 PCI 9060/MPEG AN January 14, 1996 MPEG to PCI bus Application Note _ _ _
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9060/mpegl1239l0728l0312+7sgs l282l0936l11616l99600x00000404l1198l1322
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D0807
Abstract: C0702 D0801 D0806 R0807 T0803 D0808 D0802 RDD0804 C0705
Contextual Info: PLX Technology PCI9060 Demo Board REV 1 1 2 3 4 5 6 7 8 9 10 11 Schematics 06/16/96 Title Page PCI9060, EEPROM 80960CA CPU Local Bus Control SRAM FLASH EPROM, UART 82596CA Ethernet Controller Ethernet Physical Layer PCI Bus Connector Reset, Test Headers Capacitors, Resistors
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pci906080960ca82596cau0101+1220v8ru0102d0807c0702d0801d0806r0807t0803d0808d0802rdd0804c0705
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16V8-10
Abstract: U0801A
Contextual Info: PowerPC 403 to PCI 9060ES Application Note PCI 9060/403 AN May 10, 1996 Version 0.4 PowerPC 403 to PCIbus Application Note Features_ • • • • Embedded system containing PowerPC 403 with a PCIbus interface PCI 9060ES chip supports master, slave and PCI
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9060es403local403gcpci9060es+5100ns150ns200ns16v8-10u0801a
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UPD720101
Abstract: fb11 OSC48MHz A11136 UPD720101F1-EA8 AD27 AD29 AD30 osc48m ISG-2UE-00071
Contextual Info: 4 3 5V 3.3V AD17 CBE20 C IRDY0 DEVSEL0 PERR0 SERR0 CBE10 AD14 AD12 AD10 AD8 AD7 AD5 AD3 AD1 PAR FRAME0 IRDY0 TRDY0 STOP0 IDSEL DEVSEL0 REQ0 GNT0 PERR0 SERR0 INTA0 INTB0 INTC0 PCLK PCIRST0 PME0 AD18 AD16 FRAME0 TRDY0 STOP0 PAR AD15 AD13 AD11 3.3V 132 96 129
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cbe20cbe10upc29l33tblm21pg600sn1+12150ufupd720101et-0143eisg-2ue-00071fb11osc48mhza11136upd720101f1-ea8ad27ad29ad30osc48m
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68040* part numbering
Abstract: 93CS46 SR96 L16 eeprom Motorola 68040 Pal programming 10B5
Contextual Info: Go to next Section: Designing a PCI Memory Board Return to Table of Contents Using the Motorola 68040 with the PCI 9060 Schematics etc. PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _
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pci9060/68040pci906032-bit100ns+9200ns300ns68040* part numbering93cs46sr96l16 eeprommotorola 68040pal programming10b5
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16V8-10
Abstract: semiconductor ad 5.9 u0304 R0801 74ACT74 LD11 LD12 U0801A LA17 MXA0 A10
Contextual Info: ECN HISTORY |LINK |N2.SCH |N3.SCH |N4.SCH |N5.SCH |N6.SCH |N7.SCH SPARE GATES: DESCRIPTION DATE REV 1 - 01/24/96 REV 2 -CHANGED DRMMUX 2/17/96 APPROVAL PU0101 1 PU0102 PU0103 12 11 D P R U0303B Q 9 CLK C L 1 3 Q 8 74ACT74 PU0104 APPROVALS DATE PLX TECHNOLOGY
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pu0101pu0102pu0103u0303b+1374act74pu0104powerpc/pci9060es220uf16v8-10semiconductor ad 5.9u0304r0801ld11ld12u0801ala17mxa0 a10
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0x9050 0x10b5
Abstract: 8BA22 LA2780 PLXMON95 10B5 BD28 MACH210 NM93CS46 9050RDK PLX9050
Contextual Info: PCI 9050RDK Development Kit Manual Version 1.2 January 28, 1998 Product Sales: 1- 800 -759-3735 Fax: 1- 408-774-2169 Email: info@plxtech.com Web and FTP Site: //www.plxtech.com T E C H N O L O G Y Table of Contents Preface . vii
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9050rdk9050rdk-m0020x9050 0x10b58ba22+7la2780plxmon9510b5bd28mach210nm93cs46plx9050
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787616-1
Abstract: OSC48MHz NEC A37 PCICON62 NEC AMC UPD720101 NEC A61 A37 diode LT1086CM R58 B48
Contextual Info: 3 DEVSEL0 PERR0 SERR0 CBE10 AD14 AD12 AD10 AD8 AD7 AD5 AD3 AD1 PAR FRAME0 IRDY0 TRDY0 STOP0 IDSEL DEVSEL0 REQ0 GNT0 PERR0 SERR0 INTA0 INTB0 INTC0 PCLK PCIRST0 PME0 AD18 AD16 FRAME0 TRDY0 STOP0 PAR AD15 AD13 AD11 3.3V 132 96 129 6 97 92 54 126 144 55 7 125
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cbe10cbe30cbe20cbe00+13pcicon62150ufblm21pg600sn1upd720101et-0143e787616-1osc48mhznec a37nec amcnec a61a37 diodelt1086cmr58 b48
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AD14
Abstract: PCICON62B AD27 AD17 AD29
Contextual Info: 1 2 3 4 5 6 7 8 A A CLK TDD VCC VCC J0601 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 REQ# AD[0.31] AD[0.31] AD31 AD29 AD27 AD25 B C/BE3# AD23 AD21 AD19 AD17 C/BE2#
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j0601j0602req64pcicon62a+6pci9060/dramad14pcicon62bad27ad17ad29
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la2 d2 timer
Abstract: L0936 Header 13X2 l0728 PIN DIAGRAM OF IC LM7805 U0202 L9960 STI3400 L1239 L4204
Contextual Info: Go to next Section: PCI to Local Bridge Performance Study Return to Table of Contents Using the PCI 9060 without a CPU SGS Thomson MPEG with PCI 9060 PLX Technology SGS PCI MPEG Board Engineering Changes 07/15/96 1. The PCI9060 always reads long words, even when the local bus is configured for 16-bits. Modify the BUSCTL
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pci906016-bitsla2 d2 timerl0936+8header 13x2l0728pin diagram of ic lm7805u0202l9960sti3400l1239l4204
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8BA22
Abstract: header 20X2 PCICON62B ba21 PCI9050 LA10 LA12 LA15 LA16 LA17
Contextual Info: A B C D E 2 CLK 2 PAR 2 IDSEL C/BE0# C/BE1# C/BE2# C/BE3# 2 RST# 2 INTA# 2 STOP# 2 PERR# 2 SERR# 2 FRAME# 2 DEVSEL# 2 IRDY# 2 TRDY# 2 LOCK# 2 2 2 2 2 AD[31.0] E 5V E 1 5 8 4 1 R2 2 2 10k R1 10k PE PRE CS SK DI GND VCC DO U3 93CS46 1 2 JUMPER JP3 5V 6 7 1
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93cs46irq12irq15irq14+14mstr16isa16b9050rdk74ac208ba22header 20x2pcicon62bba21pci9050la10la12la15la16la17
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AD14
Abstract: AD27 PCICON62B AD-12 AD17 AD29 AD12 J0701
Contextual Info: 1 2 3 4 5 6 7 8 2 CLK TDD VCC VCC J0701 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 A 2 2 REQ# AD[0.31] AD[0.31] AD31 AD29 2 AD27 AD25 C/BE3# AD23 AD21 AD19 B AD17
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j0701j0702ad2n62bpcicon62a+7ad14ad27pcicon62bad-12ad17ad29ad12
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AD14
Abstract: PCICON62B electronic lock schematic diagram AD-12 AD11 AD17 AD27 AD29 AD252 AD10
Contextual Info: CLK 2 INTA# 2 RST# 2 GNT# 2 IDSEL 2 TDD VCC VCC J0601 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 +3.3V 2 2 REQ# AD[0.31] AD[0.31] AD31 AD29 AD27 AD25 2 C/BE3#
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j0601req64pcicon62apowerpc/pci9060es+10ad14pcicon62belectronic lock schematic diagramad-12ad11ad17ad27ad29ad252ad10
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1N4148/2 pin connector sip
Abstract: ACT04 MOTOROLA 1N4148 D0805 pal programming sw dip-3 80960CA 15 pin through hole d sub connector 16v8h DIODE MOTOROLA B33 D0805
Contextual Info: Go to next Section: Using the Motorola 68040 Return to Table of Contents Using the Intel 80960 CA with the PCI 9060 PLX evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000
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pci90600x000000000x000000020x00000004+14100ns200ns300ns80960capclk1-331n4148/2 pin connector sipact04 motorola1n4148 d0805pal programmingsw dip-315 pin through hole d sub connector16v8hdiode motorola b33d0805
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L0936
Abstract: L0988 L9960 L1239 STI3400 L1462 E442 L1105 L3216 U0601
Contextual Info: Using the PCI 9060 without a CPU SGS Thomson MPEG with PCI 9060 PCI 9060/MPEG AN January 14, 1996 MPEG to PCI bus Application Note _ _ _ General Description _ Features_
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9060/mpegl0936l0988l9960+7l1239sti3400l1462e442l1105l3216u0601
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10B5
Abstract: 93CS46
Contextual Info: Using the Motorola 68040 with the PCI 9060 Schematics etc. PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _ Features_ • •
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pci9060/68040pci906032-bit100ns+4200ns300ns10b593cs46
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MPC860
Abstract: PCI9080 mpc860 users manual "Development Support" 9080RDK-860 0x10b5 DY9080 R9080 32X2 BUS49 LA10
Contextual Info: PCI 9080RDK-860 Hardware Reference Manual Release 2.0, initial publishing February 2, 1998. Copyright 1998, PLX Technology, Inc. All rights reserved. This document contains proprietary and confidential information of PLX Technology Inc. PLX . The contents of this document may not be copied nor duplicated in any form, in whole or in part,
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9080rdk-860mpc860pci9080mpc860 users manual "development support+60x10b5dy9080r908032x2bus49la10
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uPD720102
Abstract: UPD720102GC UPD720102GC-YEB-A CBE20 UPD720102GC-YEB ET-D720102-0002 D7201 D720102 NEC A37 AD27
Contextual Info: 3 Connect PCI PRSNT1# and PRSNT2# pins to GND appropriately to correctly reflect the total card power consumption. AD12 AD10 AD8 AD7 AD5 AD3 AD1 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 AD8 AD7 +3.3V AD5 AD3 GND AD1 VDD_IO ACK64# +5V +5V C/BE0# +3.3V AD6
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cbe10ack64req64cbe30+11cbe20cbe00upd720102upd720102gcupd720102gc-yeb-aupd720102gc-yebet-d720102-0002d7201d720102nec a37ad27
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code h7f
Abstract: datasheet LD9 m mah8 MDL22 MDL14 fuse 9060ES A3-12 LD11 MACH210A U0101
Contextual Info: Go to next Section: PowerPC 403 to PCI 9060ES Return to Table of Contents Designing a PCI Memory Board No CPU, DRAM Control examples PLX PCI9060 DRAM Controller Application Note Revision 1.0 September 8, 1995 PLX Technology, Inc. 625 Clyde Avenue, Mt View, California 94043
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9060espci90609060/dram100ns+11150nsbclk-33code h7fdatasheet ld9 mmah8mdl22mdl14 fusea3-12ld11mach210au0101
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