P FET Search Results

Contextual Info: ¡H C . V P 0 10 4N 6 / V P 0 10 4N 7 V P 0 10 6N 6 / V P 0 1 0 6 N 7 P-Channel Enhancement-Mode Vertical DMOS FET Quad Array Ordering Information Standard Commercial Devices Order Number / Package BV dss / B V ogs max 14-Pin P-DIP 14-Pin C-DIP* -40V 8 ÎÎ

Contextual Info: I bb53^31 0024111 53fl « A P X Philips Semiconductors Data sheet status P r e lim in a r y s p e c ific a tio n 2N5116 NAf1ER philips/1>iscre:te: P-channel J-FET date of issue July 1993 FEATURES • P-channel complement of 2N4393 • Short sample and hold aperture

SMD10P05L

Abstract: 1A 5v input 5v output regulator SMD10P05 Matsuo Tantalum 2N3904 ICL7611 Si9433DY P-channel power mosfet
Contextual Info: DESIGN SHOWCASE P-FET linear regulator has low dropout voltage P-channel MOSFETs P-FETs , though more expensive than pnp transistors, are free of the dissipation loss associated with base drive in a pnp circuit. P-FETs also have a lower saturation voltage

str 6551

Abstract: str g 6551 PowerPC-620 powerPC 620
Contextual Info: PowerPC P relim in ary D a ta Highlights PowerPC 620 RISC Microprocessor P ro d u ct D escrip tion H ighlights 6 4 - b it A d v an c e d S u p e r s c a le r P r o c e sso r: Fetch and d ispatch up to 4 in stru ction s p e r cycle Sp ecu lative execution p a st 4

Contextual Info: _ _ VP0635 VP0640 — P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package b v dss/ ^DS ON I d(ON) BV dgs (max) (min) TO-39 TO-92 TO-220 DICE+ -350V 25Q -0.4A V P 0 635 N 2 V P 0 635 N 3 V P 0 635 N 5 V P 0 635 N D -400V

Contextual Info: _ J jjjj ^ _ VP0645 VP0650 _ P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package dss/ ^DS ON ^D(ON) b v dgs (max) (min) TO-39 TO-92 TO-220 DICE+ -450V 30Q -0.2A V P 0 645 N 2 V P 0 645 N 3 V P 0 645 N 5 V P 0 645 N D

IVN6000

Abstract: IVN6000KNT IVN6000KNS IVN6000KNR
Contextual Info: IVN6000 KN Series 450V n-Channel Enhancement-mode Vertical Power MOS FETs FEATURES APPLICATIONS • H ig h s p e e d , h ig h cu rre n t s w itch in g • S w itc h in g p o w e r s u p p lie s • Inherent cu rre n t s h a rin g c a p a b ility w h en p ara lle le d

IR 536

Abstract: TE 536
Contextual Info: N E /S U 536-T DESCRIPTION FEATURES The 536 is a spe cia l purpose h ig h p e rfo r­ m ance o p e ra tio n a l a m p lifie r u tiliz in g an FET in p u t stage fo r ex tre m e ly h ig h in p u t im pedance and low in p u t current. • • • • • •

TEA-1035

Abstract: NEC 2SJ330 2SJ330 MEI-1202 TC-2465 tc2465
Contextual Info: DATA SHEET NEC P-CHANNEL MOS FIELD EFFECT POWER TRANSISTOR Ü— r 2SJ330 SWITCHING P-CHANNEL POWER MOS FET INDUSTRIAL USE DESCRIPTION The 2SJ330 is P-channel M O S Field Effect Transistor designed PACKAGE DIMENSIONS in millimeters fo r solenoid, m otor and lam p driver.

FR 151 diode

Abstract: Fly DS 100
Contextual Info: 2SK1278 FUJI POWER M OS-FET N-CHANNEL ENHANCEMENT TYPE MOS-FET F-V SERIES • Heatures lO utline D raw ings • lr elude fa st recovery diode • High voltage • Low driving p o w er ■ A p p lic a tio n s • IV o to r controlers • lr verters • C io p p o rs

ICL7611

Abstract: MAX872
Contextual Info: POWER-SUPPLY CIRCUITS Application Note 103: Jul 09, 1998 P-FET Linear Regulator Has Low Dropout Voltage P-channel MOSFETs P-FETs , though more expensive than pnp transistors, are free of the dissipation loss associated with base drive in a pnp circuit. P-FETs also have a lower saturation

bms 16s

Abstract: SWBT13 UT1553BCRTM ta306
Contextual Info: UT1553 BCRTM p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553 dual-redundant Bus p p p p p programmability p DMA memory interface with 64K addressability p Internal self-test p Radiation-hardened option available for 84-lead

Contextual Info: Sj j _ _ _ VP0104N6/VP0104N7 VP0106N6/VP0106N7 P-Channel Enhancement-Mode Vertical DMOS FET Quad Array Ordering Information BVDSS/ BVdgs R Order Number / Package d S ON (max) 14-Pin P-DIP 14-Pin C-DIP* -40V 8Q V P 0 104 N 6 V P 0 104 N 7 -60V 8Q

bcrtm

Abstract: A438 UT1553 UT1553B MIL-STD-1773 UT1553BCRTM A2 SMD MARKING CODE
Contextual Info: UT1553 BCRTM p Register-oriented architecture to enhance FEATURES p Comprehensive MIL-STD-1553 dual-redundant Bus p p p p p programmability p DMA memory interface with 64K addressability p Internal self-test p Radiation-hardened option available for 84-lead

Contextual Info: 2N4416-A N-CHANNEL FET CASE TO-7 2 2N4416 and 2N4416A a r e N - ch an n e l f i e l d - e f f e c t tr a n s is t o r s d e s ig n e d f o r g e n e r a l p u rp o se a m p l i f i e r and ch o p p e r a p p l i c a t i o n s . ABSOLUTE MAXIMUM RATINGS : 2N4416

ADR441

Abstract: ADR440 ADR444 ADR445 ADR443 adr441brz
Contextual Info: Ultralow Noise, LDO XFET Voltage References with Current Sink and Source ADR440/ADR441/ADR443/ADR444/ADR445 PIN CONFIGURATIONS Ultralow noise 0.1 Hz to 10 Hz ADR440: 1 V p-p ADR441: 1.2 μV p-p ADR443: 1.4 μV p-p ADR444: 1.8 μV p-p ADR445: 2.25 μV p-p

VOUT64

Abstract: ADR443 adr441brz ADR440 ADR441 ADR444 ADR445 ADR441ARMZ-REEL7 RP 10K AD5235
Contextual Info: Ultralow Noise, LDO XFET Voltage References with Current Sink and Source ADR440/ADR441/ADR443/ADR444/ADR445 PIN CONFIGURATIONS Ultralow noise 0.1 Hz to 10 Hz ADR440: 1 V p-p ADR441: 1.2 μV p-p ADR443: 1.4 μV p-p ADR444: 1.8 μV p-p ADR445: 2.25 μV p-p

Contextual Info: SOT89 P CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET ZVP2106Z FEATU RES * PARTM ARKIN G D E T A IL -Z V P 2 1 0 6 Z -P 1 6 FOR T Y P IC A L C H A R A C T E R IS T IC S G R A P H S S E E ZVP2106G D A TA SH EET. ABSOLUTE MAXIMUM RATINGS SYM BOL PARAMETER Drain-Source Voltage

AD520* differential amplifier

Abstract: ADR440 ADR441 ADR443 ADR444 ADR445
Contextual Info: Ultralow Noise, LDO XFET Voltage References with Current Sink and Source ADR440/ADR441/ADR443/ADR444/ADR445 PIN CONFIGURATIONS Ultralow noise 0.1 Hz to 10 Hz ADR440: 1 V p-p ADR441: 1.2 μV p-p ADR443: 1.4 μV p-p ADR444: 1.8 μV p-p ADR445: 2.25 μV p-p

ADR440

Abstract: ADR441 ADR443 ADR444 ADR445 adr441brz
Contextual Info: Ultralow Noise, LDO XFET Voltage References with Current Sink and Source ADR440/ADR441/ADR443/ADR444/ADR445 PIN CONFIGURATIONS Ultralow noise 0.1 Hz to 10 Hz ADR440: 1 V p-p ADR441: 1.2 μV p-p ADR443: 1.4 μV p-p ADR444: 1.8 μV p-p ADR445: 2.25 μV p-p

Contextual Info: V P 0300 ÇfySupertex inc. P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Standard Commercial Devices B ^dss 1 Order Number / Package ^DS O N *D(ON) BV dgs (max) (min) TO-39 TO-92 -30V 2.5S2 -1.5A V P 0 3 00 B V P 0 3 00 L High Reliability Devices

Contextual Info: S u p e r t e x in c TP0616 TP0620 Low Threshold . P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package R DS ON b v tcs (max) -160V 120 -0.75A -2.4V TP0616N 2 T P 0616N 3 T P 0616N 5 T P0616N D -200V 12£i -0.75A -2.4V

Contextual Info: i 77 - / Supertex inc. vn246o New Product N-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information ^DS<ON> b v dgs (max 600V 20 £2 i f BVDss / 0.25A Order Number / Package TO-92 TO-243AA* VN2460N3 VN2460N8 * S a m e as S O T -8 9 P ro du ct S u p p lie d o n 2 0 0 0 p ie ce c a rrie r ta p e reels.

PC4072

Abstract: c4072
Contextual Info: V f T C ¿/PC4072 DUAL J-FET INPUT LOW-NOISE o p e r a t i o n a l a m p lif ie r NEC Electronics Inc. Pin Configurations Description T he J-FE T in p u t o p e ra tio n a l a m p lifie rs o f the/L/PC4072 are designed as lo w -n o ise versions o f the //PC4082.