O20R Search Results

Contextual Info: 1»ill 1IFV1F 1 1 U 1 ‘! S y P r • W 0 L HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V3569S F ea tu re s: ♦ True Dual-Ported memory cells which allow simultaneous access of the same memory location ♦ High-speed clock to data access

Contextual Info: 1» i l l 1 I F V 1 F III 11 Jl 1 ‘! S y P r • L HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT70V3579S F ea tu re s: ♦ True Dual-Ported memory cells which allow simultaneous access of the same memory location

A12L

Abstract: A14L IDT70V3579 IDT70V3579S
Contextual Info: HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 5/6ns max. Pipelined output mode

70V3569

Abstract: A12L A13L IDT70V3569 IDT70V3569S
Contextual Info: HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V3569S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access

Dynachip

Abstract: SR flip flop using discrete gates T flip flop pin configuration DL-5000 i33b DL5000 DL5064 DL5256 DL5528 MUX24
Contextual Info: DL5000 Family Fast Field Programmable Gate Array Features • Fast Field Programmable Gate Arrays™ Patented Active Repeater™ Architecture Data and Clock Rates up to 270 MHz Complex operations up to 200 MHz Input Block Register Setup Time 800 ps Output Block Register Clock-to-out 1.6 ns

tdc 310

Abstract: ba6l BA6R 10 35L U1
Contextual Info: HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip

ba6l

Contextual Info: HIGH-SPEED 3.3V 64K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 64K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 1K x 36 banks – 2 megabits of memory on chip

IDT70T659

Contextual Info: HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE Features ◆ ◆ ◆ ◆ ◆ ◆ Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port

10 35L U4

Abstract: 70V7589 IDT70V7589 IDT70V7589S BA5L
Contextual Info: HIGH-SPEED 3.3V 64K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V7589S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 64K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 1K x 36 banks

IDT70T659

Abstract: 9S12 CAN 9S12
Contextual Info: Š Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT70T651/9S HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE ◆ On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port

70V7519

Abstract: IDT70V7519 IDT70V7519S ba6l
Contextual Info: Š HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip

A17R-A0R

Abstract: A17L-A0L 7144
Contextual Info: HIGH-SPEED 1.8V 256/128K x 36 IDT70P3519/99 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V/2.5V/1.8V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location Low Power High-speed data access

O23R

Abstract: o32l 70V3579 A12L A14L IDT70V3579 IDT70V3579S optl p2 3.5mm
Contextual Info: Š HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V3579S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access

IDT70T3589

Abstract: IDT70T3599 70T359 70T3589
Contextual Info: HIGH-SPEED 2.5V 256/128/64K x 36 IDT70T3519/99/89S SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access

Contextual Info: Š Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT70T651/9S HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE ◆ On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port

B12 IC marking code

Abstract: 70V3599 A12L IDT70V3599 IDT70V3599S
Contextual Info: HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V3599S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access

IDT70T659

Contextual Info: HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 10/12/15ns max.

027R

Abstract: 351N 70V3579 A12L IDT70V3579 IDT70V3579S
Contextual Info: HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V I/O PRELIMINARY IDT70V3579S Features: * * * * * * True Dual-Port memory cells which allow simultaneous access o f the same memory location High-speed clock to data access

IDT70T3589

Abstract: IDT70T3599 70T3589
Contextual Info: HIGH-SPEED 2.5V PRELIMINARY 256/128/64K x 36 IDT70T3519/99/89S SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access

CY7C09569V

Contextual Info: CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3 V 16 K / 32 K x 36 FLEx36 Synchronous Dual-Port Static RAM CY7C09569V CY7C09579V ® 3.3 V 16 K / 32 K × 36 FLEx36 Synchronous Dual-Port Static RAM 3.3 V 16 K / 32 K × 36 FLEx36® Synchronous Dual-Port Static RAM

256-pin BGA drawing

Contextual Info: HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 4.2/5/6ns max.

O20R

Abstract: QX 78 O23R w 5667 O28R O25R O20L
Contextual Info: HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS FLOW-THROUGH DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V356S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access

Contextual Info: Š HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 2K x 36 banks – 4 megabits of memory on chip

70T3539M

Contextual Info: HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access – Commercial: 3.6ns 166MHz /4.2ns (133MHz)(max.)