O128 Search Results

EB-500

Abstract: 342105-1 eb500 342144-1
Contextual Info: 2 1 oopniur i«M II Mff IKOVOMTn. •m iiwmmiMr EBO0-O480-97 12-09-9 m E0OO-O128-oa t9-02-0< UH FWK NOTES: FOR PACKAGING AND L A B E L L IN S OPTIONS OF ANY PART NUMBERS L IS T E D ON T H IS DRAWING ADO THE RELEVANT P R E F IX E S AND S U F F IX E S , e . g . P L A S T iC BOX tflTH FRENCH LA8EL

CY37384

Abstract: CY37384V
Contextual Info: PRELIMINARY CY37384 UltraLogic 384-Macrocell ISR™ CPLD — tS = 5.5 ns Features • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes

d4184

Abstract: transistor N14 193 atmel application note AT6002 AT6003 AT6005 AT6010
Contextual Info: Features • High-performance • • • • • • • • • – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay Up to 204 User I/Os Thousands of Registers Cache Logic Design

3M-2520-6002-UG

Abstract: TNETX3100 HF70ACB453215T MAX232ACSE 4Mbit eeprom DIAMONDBACK TNETX4090 TNETX3110 TNETX3150 "Spanning Tree"
Contextual Info: Diamondback Management Card Schematic Description and Schematics APPLICATION REPORT: SPWA033 World Wide Broadband Access Group LAN Products May 1999 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise

K 3673

Abstract: 3673 SN 46 LS 46 LC4103 LC4103C LC4103TAB-01 LC4103TAB-02
Contextual Info: * Ordering number:ENN 5193B CMOS P-sub LC4103TAB-01, 4103TAB-02, 4103C STN LCD Dot Matrix Common Driver Preliminary Overview The LC4103 is a common driver IC for large-scale dot matrix LCD displays, It includes a 160-bit bidirectional shift register and 4-level LCD drivers. The number of bits can

5d3 diode

Abstract: 6B15 7b12 MACH Programmer transistor 7B12 2D15 PAL 007 A power generator control circuit schematic 1C12 5D10
Contextual Info: MACH 5 CPLD Family I MAC ncludes H Adv anc 5A Fam e In form ily atio n Fifth Generation MACH Architecture FEATURES ◆ High logic densities and I/Os for increased logic integration ◆ ◆ ◆ ◆ ◆ ◆ ◆ — 128 to 512 macrocell densities — 68 to 256 I/Os

PLSI 1016-60LJ

Abstract: PAL 007 pioneer pal16r8 programming algorithm PAL 008 pioneer lattice 1016-60LJ ISP Engineering Kit - Model 100 PLSI-2064-80LJ GAL16v8 programmer schematic GAL programming Guide ispLSI 2064-80LT
Contextual Info: Lattice Semiconductor Data Book 1996 Click on one of the following choices: • Table of Contents • Data Book Updates & New Products • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. ispLSI and pLSI Product Index Pins Density

Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

ic 4040

Abstract: 4040 cmos ci 4040 cmos 4040 stv 4325 O129-O135 PD16707 4040
Contextual Info: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社

Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

Contextual Info: お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジ が合併し両社の全ての事業が当社に承継されております。従いまして、本資料中には旧社

2A299

Abstract: HP3070 MArking 3A5 AMD CPLD Mach 1 to 5 MACH5-256
Contextual Info: MACH 5 FAMILY 1 FINAL COM’L: -7/10/12/15 IND: -10/12/15/20 MACH5-256 MACH5-256/68-7/10/12/15 MACH5-256/120-7/10/12/15 MACH5-256/104-7/10/12/15 MACH5-256/160-7/10/12/15 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ Fifth generation MACH architecture

marking 3B3

Abstract: 32V16 mach 1 family amd 3A10 MC5C1 MACH5 cpld amd
Contextual Info: PRELIMINARY COM’L: -7/10/12/15 IND: -10/12/15/20 The MACH5-256 MACH5-256/68-7/10/12/15/20 MACH5-256/104-7/10/12/15/20 MACH5-256/120-7/10/12/15/20 MACH5-256/160-7/10/12/15/20 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS • Fifth generation MACH architecture

Contextual Info: 1 MACH 5 FAMILY MACH 5 Family Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ ◆ ◆ ◆ ◆ ◆ ◆ Publication# 20446 Amendment/0 Rev: D Issue Date: August 1997 MACH 5 Family ◆ Fifth generation MACH architecture — 100% routable

CY37512

Abstract: CY37512V
Contextual Info: Back PRELIMINARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — tPD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

CY37384

Abstract: CY37384V cpld internal
Contextual Info: Back PRELIMINARY CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Features — tPD = 15 ns — tS = 8 ns • 384 macrocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • •

4D-13

Abstract: HP 3D6 making 5A6 3d13 3D-14 5B7 Marking i 384
Contextual Info: MACH 5 FAMILY X FINAL COM’L:-7/10/12/15 IND:-10/12/15/20 MACH5-384/MACH5LV-384 MACH5-384/120-7/10/12/15 MACH5-384/192-7/10/12/15 MACH5LV-384/184-7/10/12/15 MACH5-384/160-7/10/12/15 MACH5LV-384/120-7/10/12/15 MACH5LV-384/192-7/10/12/15 MACH5-384/184-7/10/12/15

HP3070

Abstract: 1b13 107-2-A-12 MACH5 cpld amd
Contextual Info: MACH 5 FAMILY 1 FINAL COM’L: -7/10/12/15 IND:-10/12/15/20 MACH5-192 MACH5-192/68-7/10/12/15 MACH5-192/104-7/10/12/15 MACH5-192/120-7/10/12/15 MACH5-192/160-7/10/12/15 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ◆ Fifth generation MACH architecture

CABGA

Abstract: fpga JTAG Programmer Schematics AT17 AT40K AT94K AT94S AT94S05AL AT94S10AL AT94S40AL C16107
Contextual Info: Features • Multichip Module Containing Field Programmable System Level Integrated Circuit • • • • • • • • • • • • • • • • • FPSLIC and Secure Configuration EEPROM Memory 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System

gck451

Abstract: 2818C AT40K AT40K05AL AT40K10AL AT40K20AL AT40K40AL AT40KAL XC4000 XC5200
Contextual Info: Features • Ultra High Performance • • • • • • • • • • – System Speeds to 100 MHz – Array Multipliers > 50 MHz – 10 ns Flexible SRAM – Internal Tri-state Capability in Each Cell FreeRAM – Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM

max 8770

Abstract: MOS 6526 SR299 diode 3562 SR300 IC 6994 14 pin SR300 datasheet what is product ON 4914
Contextual Info: PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT µ PD16708 300-OUTPUT TFT-LCD GATE DRIVER DESCRIPTION The µ PD16708 is a TFT-LCD gate driver equipped with 300-output lines. It can output a high-gate scanning voltage in response to CMOS level input because it provided with a level-shift circuit inside the IC circuit.

O2-A2

Abstract: Lattice Mach OX2 VCCIO11 ispMACH M4A3 M4A5-192 application note PAL 007 O64i
Contextual Info: ispMACH 4A CPLD Family High Performance E2CMOS In-System Programmable Logic FEATURES ◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families ◆ Flexible architecture for rapid logic designs ◆ ◆ ◆ ◆ ◆ ◆ ◆ — Excellent First-Time-FitTM and refit feature

Contextual Info: Features • Multichip Module Containing Field Programmable System Level Integrated Circuit • • • • • • • • • • • • • • • • FPSLIC and Secure Configuration EEPROM Memory 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System

Contextual Info: S1D17404 1. DESCRIPTION 2. FEATURES The S1D17404 is an LCD segment driver for highresolution dot-matrix panels, which incorporates 160 column driver outputs. It is designed for use in conjunction with the S1D17403/S1D17401 row driver. The S1D17404 features a wide range of LCD drive