NOR2B Search Results

TA138

Abstract: A1240XL 32 Bit loadable counter 2 bit magnitude comparator 176-CPGA "alu 4 bit" IC LM 384 gn
Contextual Info: Æ ic t â 1200XL Field Programmable Gate Arrays Features • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Datapath Performance at 135 MHz • Replaces up to 200 TTL Packages 10 ns Clock-Out speeds • Replaces up to eighty 20-Pin PAL Packages

equivalent of transistor tt 2148

Abstract: equivalent of transistor tt 2146 equivalent for transistor tt 2146 transistor TT 2146 TT 2146 M4 A4 TPC1280 TT 2146 M4 D3 TRANSISTOR TT 2158 TT 2146 M4 G4 str z 2154
Contextual Info: TPC12 SERIES CMOS FIELD-PROGRAMMABLE GATE ARRAYS SRFS002C - D3963, DECEMBER 1991 - REVISED FEBRUARY 1993 • Three Arrays With Increased Densities • Up to 8000 Equivalent Gate Array Gates • • Supported by Tl Action Logic System TI-ALS Software •

CB4CLE

Abstract: cb4re CB8CLED cb8cle CB4CLED X74-160 x4202 CB16CE sr4cled 2 bit magnitude comparator using 2 xor gates
Contextual Info: ON LIN E R LIBRARIES G UI DE T ABL E OF CONT ENT S INDEX GO T O OT HER BOOKS 0 4 0 1410 Copyright 1993-1995 Xilinx Inc. All Rights Reserved. Contents Chapter 1 Xilinx Unified Libraries Overview .

LC1 D12 wiring diagram

Abstract: vhdl code for 8 bit ODD parity generator 74139 Dual 2 to 4 line decoder TTL XOR2 tig ac inverter circuit cd4rle LC1 D12 P7 CB4CLED sr4cled CB16CE
Contextual Info: Libraries Guide Xilinx Unified Libraries Selection Guide Design Elements ACC1 to BYPOSC Design Elements (CAPTURE_SPARTAN2 to DECODE64) Design Elements (F5MAP to FTSRLE) Design Elements (GCLK to KEEPER) Design Elements (LD to NOR16) Design Elements (OAND2 to OXOR2)

xc3000 xact

Abstract: orcad schematic symbols library 1736a 3020p diode c2s DRC 110U keyboard schematic xt synopsys Platform Architect DataSheet ts08 x2547
Contextual Info: ON LIN E R DEVELOPMENT SYSTEM REFER E NCE G UI DE VOL UM E 1 TABL E OF CONT ENT S INDEX GO T O OT HER BOOKS 0 4 0 1405 Copyright 1990-1995 Xilinx Inc. All Rights Reserved. Contents Chapter 1 The XACT Design Manager Online Help .

Contextual Info: Order this data sheet by H4C/D MOTOROLA H SEMICONDUCTOR “ TECHNICAL DATA Advance Information H4C SERIES CMOS ARRAYS and the CDA™ ARCHITECTURE H IG H P ER FO R M A NC E T R IP L E LAYER M ETAL S U B -M IC R O N CMOS ARRAYS The s u b -m ic ro n H 4C S e rie s ’ " CM OS gate array fa m ily and th e new

TA138

Abstract: TA280 3SB24 TA1225A 176-CPGA dece2x4
Contextual Info: ACTEL CORP Æ Ic M b?E » I • 01^24^ DDDGÔ33 TS1 ■ ACT ACT 2 Field Programmable Gate Arrays Features Description • The ACT™ 2 family represents Actel’s second generation of field programmable gate arrays FPGAs . The ACT 2 family presents a two-module architecture, consisting of C-modules and S-modules.

2 bit magnitude comparator

Abstract: dece2x4 TA194 TA688 4 bit identity comparator AO11 TA164 2-bit down counter TA161 DLM8
Contextual Info: Accelerator Series Macro Library – Tables of Hard, Soft, and TTL Macros Hard Macros—Combinatorial Modules Function Macro Description Combinatorial Logic Module CM8 Combinational Module Full ACT 3 Logic Module Sequential Logic Module DFM8A 4-bit D-Type Flip-Flop with Multiplexed Data, active low Clear, and active

AO4A

Abstract: AO11 DFC-1 dl2d AO2B cy2b OR5B
Contextual Info: Integrator Series Hard Macro Library – Graphical Symbols The following illustrations show all the available hard macros. The Actel Macro Library Guide contains module count, combinability, and pin loading information of each hard macro. It also includes a complete truth table for each macro.

Hp 4619

Abstract: Serial NAND A1225 A1240 A1280 CQFP 256 PIN actel 81H13 actel a1240 A1280-1 2a1280
Contextual Info: SBE AC TEL CORP D • OnEHTb DGDDMGS Mb3 ■ ACT ACT 2 Field Programmable Gate Arrays Features • Up to 8000 Gate Array Gates 20,000 PLD /LC A ™ equivalent gates • Replaces up to 210 T T L Packages • Replaces up to 69 20-Pin PA L Packages • Design Library with over 250 Macros

Actel A1020

Abstract: A1020 Y A1010 A1020 A1020A C3254 CNT4A ACTEL A1010A A1010 actel DLM8
Contextual Info: ACTEL Æ CORP 34E § ACT 1 Field Programmable Gate Arrays c M 1 3 WÊ OiqgMqb ' 0000156 Ô 13ACT T—46—19—11 technology. The unique architecture offers gate array flexibility, high performance, and instant turnaround through user programming. Device utilization is typically 95% o f available logic

XC6200

Abstract: 4x4 calculator
Contextual Info: K x i l i n XC6200 Field Programmable Gate Arrays x June 1, 1996 Version 1.0 Advance Product Specification Features • • Advanced Processor-Compatible Architecture - FastMAP interface allows direct processor read/ write access to all internal registers in user design

54SXA

Contextual Info: Macro Library Guide July 2000 For more information about Actel’s products, call 888-99-ACTEL or visit our Web site at http://www.actel.com Actel Corporation • 955 East Arques Avenue • Sunnyvale, CA USA 94086 U.S. Toll Free Line: 888-99-ACTEL • Customer Service: 408-739-1010 • Customer Service FAX: 408-522-8044

MCR 22-8 transistor power

Abstract: Transistor motorola 418 10146 1987 carrier A022H on 5295 equivalents HDC031 Mustang 300 HDC011 HDC016 HDC049
Contextual Info: Order this data sheet by HDC/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA HIGH PERFORMANCE TRIPLE LAYER METAL HDC SERIES CMOS ARRAYS 1.0 MICRON CMOS ARRAYS Built on a 1.0 micron, triple-layer metal CMOS process, the HDC Series represents a significant advancement in microchip technology.

Contextual Info: h /99, æ & c M ! ACT 3 Field Programmable Gate Arrays Features Preliminary Description 10 ns Clock-to-Output Times The ACT 3 family, based on Actel’s proprietary PLICE antifuse technology and 0.8-micron double-metal, double-poly CMOS process, offers a high-performance programmable solution

Contextual Info: ACT 2 Field Program m able Gate Arrays Features • Up to 8000 Gate A rray Gates 20,000 P L D / L C A ™ equivalent gates • Replaces up to 210 T T L Packages • Replaces up to 69 20-Pin P A L Packages • Design Library with over 250 Macros • Single-Module Sequential Functions

100CPGA

Contextual Info: ACT 2 Field Programmable Gate Arrays F e a tu re s • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates • Datapath Performance at 105 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages • Two In-Circuit Diagnostic Probe Pins Support Speed

TA138

Abstract: DLM8 TPC-ALS-249 TPC1020B 4584P TA273 CNT4A
Contextual Info: TPC10 SERIES CMOS FIELD-PROGRAMMABLE GATE ARRAYS S R FS 001F - D3864, DECEM BER 19B9 - R EVISED FEBRUARY 1993 • • Four Arrays With up to 2000 Usable Equivalent Gates Tl Action Logic System TI-ALS Software for: - ViewLogic™ - Mentor™ - OrCAD/SDT III ™

TA688

Abstract: 7input and gate ao1b AO11 TA164 TA-191 TA153 TA190 DLM8 TA273
Contextual Info: Integrator Series Macro Library – Tables of Hard, Soft, and TTL Macros Hard Macros—Combinatorial Modules Function Macro Description Combinatorial Logic Module CM8 Combinational Module Full 1200XL and 3200DX Logic Module Sequential Logic Module DFM7A

dram verilog model

Abstract: MC68HC11RM F645D verilog code to generate square wave Verilog code of state machine for 16-byte SRAM 7908 motorola pal spi verilog code 16 bit CISC CPU motorola bubble memory controller MPA1000
Contextual Info: MOTOROLA SEMICONDUCTOR GENERAL INFORMATION APPLICATION NOTE 68030 DRAM Controller Design Using Verilog HDL by Phil Rauba, Motorola Field Applications Engineer Purpose This article is intended to give a hardware engineer insight into the design methodology of using the Verilog Hardware

AOI21

Abstract: OAI22 32X72 equivalent to TRANSISTOR BC 187 ao21 AN1521 low noise transistor bc 179 OMPAC wirebond die flag lead frame using NAND gate construct an inverter
Contextual Info: Order this Data Sheet by H4CP/D MOTOROLA SEMICONDUCTOR H4CPlus SERIES TECHNICAL DATA Product Data Sheet H4CPlus SERIES CMOS ARRAYS The new H4CPlus Series arrays feature new 3.3V, 5V and mixed-voltage capability, high-speed interfaces, and analog PLLs for chip-to-chip clock skew

XC6200

Abstract: p61 s43 XC6264 w1p77 w56 transistor BUF C038 N48 pqfp Package Typ P194 B1 121 W97 diode ak38
Contextual Info:  XC6200 Field Programmable Gate Arrays Table Of Contents Features Description Architecture Logical and Physical Organization Additional Routing Resources Magic Wires Global Wires Function Unit Cell Logic Functions Routing Switches Clock Distribution Clear Distribution

grid tie inverter schematics

Abstract: Xilinx counter cb16ce X6556 grid tie inverter schematic diagram grid tie inverter schematic Power INVERTER schematic circuit XC9000 CB16CE CB16CE counter xilinx cd4re
Contextual Info: ON LIN E R XEPLD SCHEMATIC D ESI G N G UI DE TABL E OF CONT ENT S INDEX GO T O OT HER BOOKS XEPLD Schematic Design Guide Getting Started with Schematic Design Design Entry Techniques Controlling Design Implementation Design Applications Common Questions and

CB4CLED

Abstract: x74_194 sr4cled CB16CE cd4re 2 bit magnitude comparator using 2 xor gates CB16CLE cd4rle 74139 Dual 2 to 4 line decoder TTL 7400
Contextual Info: ON LIN E R LIBRARIES G UI DE T ABL E OF CONT ENT S INDEX GO T O OT HER BOOKS 0 4 0 1410 Xilinx XC7000 and XC9000 Libraries Selection Guide Design Elements X2845 Index Libraries Guide Libraries Guide Printed in U.S.A. Libraries Guide R , XACT, XC2064, XC3090, XC4005, and XC-DS501 are registered trademarks of Xilinx. All XC-prefix