NDEF Search Results

Contextual Info: RF430CL330H www.ti.com SLAS916A – NOVEMBER 2012 – REVISED JUNE 2013 DYNAMIC NFC INTERFACE TRANSPONDER FEATURES 1 • • 2 • NFC Tag Type 4 ISO14443B Compliant 13.56-MHz RF Interface Supports up to 848 kbps SPI or I2C Interface to Write and Read NDEF

Contextual Info: RF430CL330H www.ti.com SLAS916 – NOVEMBER 2012 DYNAMIC NFC INTERFACE TRANSPONDER FEATURES 1 • • 2 NFC Type-4 Tag ISO14443B Compliant 13.56-MHz RF Interface Supports up to 848 kbps • • SPI or I2C Interface to Write and Read NDEF Messages to Internal SRAM

Contextual Info: DLP-RF430BP BoosterPack User’s Guide FEATURES: • • • • • • • • • Texas Instruments RF430CL330H, Rev D Silicon ISO14443B Compliant 13.56MHz RF Interface Supports up to 848 Kbps NFC Tag Type 4 Compliant 3K SRAM Bytes Available for NDEF Message Storage

nfc PN544 application note

Abstract: AN11032 ICODE SLI-S
Contextual Info: AN11032 NXP Type ICODE Tag Operation Rev. 1.1 — 1 July 2011 202211 Application note COMPANY PUBLIC Document information Info Content Keywords NFC Forum, NFC data mapping, NFC Type ICODE Tag, NFC-enabled Tag, NDEF, ICODE SLI, ICODE SLI-S, ICODE SLI-L, ICODE SLIX,

nfc pcb antenna

Abstract: SLAS916 type 4 tag RFID chip i2c 848kbps texas instruments RF430 JESD48
Contextual Info: RF430CL330H www.ti.com SLAS916 – NOVEMBER 2012 DYNAMIC NFC INTERFACE TRANSPONDER FEATURES 1 • • 2 NFC Type-4 Tag ISO14443B Compliant 13.56-MHz RF Interface Supports up to 848 kbps • • SPI or I2C Interface to Write and Read NDEF Messages to Internal SRAM

Contextual Info: RF430CL330H www.ti.com SLAS916A – NOVEMBER 2012 – REVISED JUNE 2013 DYNAMIC NFC INTERFACE TRANSPONDER FEATURES 1 • • 2 • NFC Tag Type 4 ISO14443B Compliant 13.56-MHz RF Interface Supports up to 848 kbps SPI or I2C Interface to Write and Read NDEF

Contextual Info: DLP-RF430BP BoosterPack User’s Guide FEATURES: • • • • • • • • • Texas Instruments RF430CL330H, Rev D Silicon ISO14443B Compliant 13.56MHz RF Interface Supports up to 848 Kbps NFC Tag Type 4 Compliant 3K SRAM Bytes Available for NDEF Message Storage

TC55188

Abstract: TC55188T-25 TC55188T-20 TC55188T
Contextual Info: •»ilK 2 - W A Y 4,096 W ORDS x 18 BITS/8,192 WORDS x 18 BITS CMOS STATIC CACHE DATA RAM DESCRIPTION The TC55188T is a 147,456bits high-speed static RAM which can be user-configured either a s 2-way 4,096 words by 18 bits or as 8,192 words by 18 bits. It is provided with a byte control, on-chip

Contextual Info: M O SEL V IT E L IC V53C8258L UL TRA-HIGH SPEED, 3.3 VOLT256K X 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM PR&BMBBOtt HIGH PERFORMANCE 60 Max. RAS Access Time, tRAC 60 ns Max. Column Address Access Time, (t^M ) 30 ns Min. Extended Data Out Page Mode Cycle Time, (tPC)

Ba 33 bco

Contextual Info: Direct RDRAM RAMBUS TM 32/36-M bit 256K x16/18x8d ADVANCE INFORMATION O verview The R am bus Direct RDRAM is a general p u rp o se high-perform ance m em ory device suitable for use in a broad range of applications including com puter mem ory, graphics, video, an d any other application

sle 66r01p

Abstract: SLE66R01P 66R01L 66R01P nfc antenna design NXP 14443-3 type A command read write 66R01PN SLE66 murata nfc antenna NFC Tags
Contextual Info: my- d mov e my- d™ mov e N FC S LE 66 R01 P S LE 66 R01 P N Intelligent 1216 bit EEPROM with Contactless Interface compliant to ISO/IEC 14443-3 Type A and support of NFC Forum™ Type 2 Tag Operation Sh o rt P ro d u c t I n fo r m a ti o n 2011-11-24

Contextual Info: DATA SHEET Part No. MN63Y1210A Package Code No. SSOP016-P-0225E Publication date: June 2013 Ver. AEM 1 Contents Chapter 1 Overview . 9 1.1

lux meter chip

Contextual Info: VISHAY Vishay Telefunken ▼ IrDA Standard - Physical Layer Specification In SIR mode, the data is represented by optical pulses between 1.6 ps and 3/16 of the bit length of the RS232 data pulse in SIR mode. Pulselength reduction is also applied in the higher fre­

POS system

Abstract: ne 556 timer COP684EK COP688EK COP884EK COP888EK COP984EK COP988EK
Contextual Info: ß COP888EK 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, Comparator, and Single-slope A/D Capability General Description The C O P 888E K ROM based m icrocontrollers are highly in­ tegrated COP8 Feature core devices w ith 8k m em ory and advanced features including a M ulti-Input C om parator and

Contextual Info: Advance information Features • Intelliw att active p o w e r red u ction circuitry • Easy m em o r y exp an sion w ith CEI, CE2, OË in p uts • 1.6 5 V to 1.9 5 V op eratin g range 0ESD 8 -7 • TTL/LVTTL-com patible, three-state I /O • JEDEC registered packaging

16F5

Abstract: 4c1m16
Contextual Info: Preliminary information Features • 1024 refresh cycles, 16 ms refresh interval • Organization: 1,048,576 words x 16 bits • High speed - 50/60 ns RAS access time - 20/25 ns fast page cycle time - 13/17 ns CAS access time • Low power consumption - RAS-only o r ¿AS-before-ftAS refresh

29F080

Abstract: S29F080
Contextual Info: Preliminary information Features • O rg a n iz a tio n : 1M x 8 • S ecto r a rc h ite c tu re - Sixteen 64K byte sectors - Equal sector architecture - Erase any com bination o f sectors or full chip • Single 5 .0 ± 0 .5 V p o w e r s u p p ly f o r r e a d / w r ite o p e ra tio n s

Contextual Info: M24SR64-Y Dynamic NFC/RFID tag IC with 64-Kbit EEPROM, NFC Forum Type 4 Tag and I²C interface Datasheet - production data Package • 8-lead small-outline package SO8 ECOPACK 2 SO8 (MN) UFDFPN8 (MC) TSSOP8 (DW) • TSSOP8 ECOPACK®2 • UFDFPN8 ECOPACK®2

Contextual Info: IBM11T4645MP IBM11T8645MP 4M /8M x 64 144 PIN SO DIMM Features • Au contacts • 144 Pin JEDEC Standard, 8 Byte Small Outline Dual In-line Memory Module with 8 Byte busses • Optimized for byte-write non-parity applications • 4M/8Mx64 Extended Data Out SO DIMM

Contextual Info: IBM13T4644MPC 4M x 64 SDRAM SO DIMM Features • 144 Pin emerging JEDEC Standard, 8 Byte Small Outline Dual-In-Iine Memory Module • Programmable Operation: - CAS Latency: 2, 3 - Burst Type: Sequential or Interleave - Burst Length: 1, 2, 4, 8, Full-Page (FullPage supports Sequential burst only)

Contextual Info: <991 in te i 80C188XL20,16,12, 10 16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR • Low Power, Full Static Version of the 80C188 Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I/O ■ Operation Modes Include: — Enhanced Mode — DRAM Refresh Control Unit

block diagram for spy ear

Abstract: m30c design of spy ear spy ear datasheet COP87L84BC COP87L88EB COP87L88RB COP87L89EB COP87L89RB COP888EB
Contextual Info: Semiconductor ß COP87L88EB/RB Family 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory, CAN Interface, 8-Bit A/D, and USART General Description The C O P 87L88EB/R B Fam ily OTP (One Tim e program ­ mable m icrocontrollers are highly integrated COP8 Fea­

COP87L88RDV-XE

Abstract: TE-32 COP87L88GD COP87L88RD COP888GD V44A
Contextual Info: ß COP87L88GD/RD Family 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory and 8-Channel A/D with Prescaler General Description The C O P87L88G D /R D O TP (One Time Program m able Fam ily m icrocontrollers are highly integrate! COP8 Fea­ ture core devices w ith 16k or 32k mem ory and advanced

SY2128

Abstract: Synertek 2128-3 RAM SYP2128-1 SYP2128-4 28L-1 SYP21
Contextual Info: SY2128 2048 x 8 Static Random Access Memory S v n e rte k . Features • • • • • • 1 0 0 nsec M a x im u m A ccess T im e F u lly S ta tic O pe ration : No C locks o r S trob es R equired A u to m a tic CE P o w e r D ow n Id e n tic a l C ycle a n d A cce ss T im e s