MNEMONIC Search Results

Instructions of TMS320C54X

Abstract: tms320c54x MEMORY MAPPED REGISTERS IMR IFR 7688 memory chip MAS 10 RCD spru131 tms320c54x MEMORY MAPPED REGISTERS ST0 ST1 TMS320C54x, instruction set TMS320 XDS510 AR-70
Contextual Info: TMS320C54x DSP Reference Set Volume 2: Mnemonic Instruction Set Literature Number: SPRU172B June 1998 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest

0x19C

Abstract: RCPU 0X177 0x37
Contextual Info: APPENDIX A INSTRUCTION SET LISTINGS This appendix lists the instruction set implemented in the RCPU, sorted by mnemonic. Reserved bits are shaded. Table A-1 Complete Instruction List Sorted by Mnemonic Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

countdown timer code for 8051 with keypad

Abstract: intel 8051 opcode sheet DS2250 DS2250T DS5000 DS5000FP DS5000T DS5000TK PC15 interfacing of magnetic stripe with 8051
Contextual Info: USER’S GUIDE SECTION 19: INSTRUCTION SET DETAILS INSTRUCTION CODE ARIT ITHM METIC OP PERA ATION MNEMONIC HEX BYTE CYCLE EXPLANATION D7 D6 D5 D4 D3 D2 D1 D0 ADD A, Rn 1 1 n2 n1 n0 28–2F 1 1 A = (A) + (Rn) ADD A, direct a7 a6 1 a5 a4 a3 1 a2 a1 1 a0 25

FRCT

Abstract: C54CM SPRU375 TMS320 SC 4340 SP0305 TMS320C54x fir filter applications AC05F
Contextual Info: TMS320C55x DSP Mnemonic Instruction Set Reference Guide Literature Number: SPRU374E April 2001 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest

mnemonic

Abstract: instruction list MSM66101 MSM66507
Contextual Info: This version: Jan. 1998 Previous version: Nov. 1996 E2E1025-27-Y2 ¡ Semiconductor OLMS-66K SERIES INSTRUCTION LIST OLMS-66K SERIES INSTRUCTION LIST MSM66101, 66201/66P201, 66207/66P207, 66507/66P507, 66509/66P509 Data Move Mnemonic Word move Word load Word move (Word store)

33dst

Abstract: 34CD SPRU131 TMS320 XDS510 SC 4105 LMS 339 XPC header
Contextual Info: TMS320C54x DSP Reference Set Volume 2: Mnemonic Instruction Set Literature Number: SPRU172A August 1997 Printed on Recycled Paper Running Title—Attribute Reference IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any

80960MC

Contextual Info: Instruction Reference 17 CHAPTER 17 INSTRUCTION REFERENCE This chapter provides detailed information about each of the instructions for the 80960MC processor. To provide quick access to information on a particular instruction, the instructions are listed alphabetically by assembly-language mnemonic. An explanation of the format and

HP1650A

Abstract: a92b HP1651A HP16510A FD08 005D c343 diode HP16500A AN-688 C1995
Contextual Info: National Semiconductor Application Note 688 Laura Johnson July 1990 OVERVIEW The DP8344 BCP Inverse Assembler is a software package for use in a Hewlett Packard Logic Analyzer It was developed by National Semiconductor’s Arlington Design Center to allow disassembly of the DP8344 op-code mnemonics

740-Family

Contextual Info: MITSUBISHI MICROCOMPUTERS 740 Family Reference Programs 2.4 Rotate Shift 1 Rotate One Bit Left (mnemonic ROL) The ROL instruction puts the contents of Accumulator A or Memory M and Carry Flag C together as a 9-bit row and rotates the contents one bit to the left. Then, the contents of Carry Flag C are stored

4 Signal s ZiVA

Contextual Info: 4 Signal Descriptions This chapter describes the signals that comprise the external physical interface to the ZiVA decoder. The information presented for each signal includes the signal mnemonic and name, type input, output, or bidirectional , and description. (Note: The overbar symbol denotes active

tlcs-870 series instruction set

Abstract: TLCS-870 MNEMONIC TLCS-870 GG 06 00000-0FFFFH 1110-0000-XXXX tlcs870 mnemonic
Contextual Info: TO SH IB A 1.6 TLCS-870/X Description of Instruction 1 D A T A TRANSFER, E X C H A N G E MNEMONIC LD A, r O BJECT CODE Binary Hex-decimal 0101 Orrr 5r c Y c FLAG OPERATION J F ZF CF HF SF VF 1 A < -r L E 1 7, The contents of the register r are loaded into the accumulator. The zero flag is set to “ 1” if r = 00h ;

7654h

Abstract: TLCS-900 1234H 2654H TLCS-900H
Contextual Info: T O S H IB A TLCS-900/H CPU OR dst, src < Logical OR > O peration Description : dst<—dst OR src : Ors the contents of dst w ith those of src and loads the resu lt to dst. Truth table A B A OR 1 1 1 1 1 1 1 B D etails Size Byte Word Mnemonic Code Long word_

2431EA

Abstract: bcx 16 b2790 powerpc 476
Contextual Info: MPCxxx Instruction Set This chapter lists the MPCxxx instruction set in alphabetical order by mnemonic. Note that each entry includes the instruction formats and a quick reference ‘legend’ that provides such information as the level s of the PowerPC architecture in which the instruction may

8 bit left right shift register

Abstract: MCF5200 PC111
Contextual Info: SECTION 4 INTEGER INSTRUCTIONS This section describes the integer instructions for the ColdFire Family. A detailed discussion of each instruction description is arranged in alphabetical order by instruction mnemonic. MOTOROLA MCF5200 FAMILY PROGRAMMER’S REFERENCE MANUAL

Contextual Info: SECTION 5 SUPERVISOR PRIVILEGED INSTRUCTIONS This section contains information about the supervisor (privileged) instructions for the ColdFire Family. Each instruction is described in detail with the instruction descriptions arranged in alphabetical order by instruction mnemonic.

5A6H

Abstract: intel atom microprocessor 5a1h 80960Cx i960 Cx Instruction Set Quick Reference i960 Cx Processor Instruction Set Quick Reference om-1 st stt 128 transistor mark code g8 610H
Contextual Info: Instruction Set Reference 1 This chapter provides detailed information about each instruction available to the i960 Jx processor. Instructions are listed alphabetically by assembly language mnemonic. Format and notation used in this chapter are defined in Section 1.1, “Notation” pg. 1-1 .

C908QY2

Abstract: MC68H MC68HC08 MC68HC908QY4 pc keyboard CIRCUIT wire diagram PK-HC08QY4
Contextual Info: MC68HC908QY4 Easy Reference Mnemonic Description Operation Flags PTB7 2 15 PTB0 ADC Add with Carry A ← A + (M) + (C) V, H, N, Z, C PTB6 3 14 PTB1 ADD Add without Carry A ← (A) + (M) V, H, N, Z, C PTA5/OSC1/AD3/KBI5 4 13 PTA0/AD0/TCH0/KBI0 AIS Add Immediate Value to Stack Pointer

mnemonic

Abstract: OLMS-66K
Contextual Info: O K I Semiconductor OLMS-66K SERIES INSTRUCTION LIST for nX-8/500S Core OLMS-66K SERIES INSTRUCTION LIST (for nX-8/500S Core) MSM66589/66P589/66Q589 Data Transfer Instructions Mnemonic Function L 16-bit load LB 8 -b it load ST 16-bit store STB 8 -b it store

mnemonic

Abstract: M66507
Contextual Info: O K I Semiconductor OLMS-66K SERIES INSTRUCTION LIST OLMS-66K SERIES INSTRUCTION LIST MSM66101,66201/66P201, 66207/66P207, 66507/66P507,66509/66P509 Data Move Mnemonic I L | ST ! MOV Word move Word store Word move CLR ! FILL* : Word fill Word clear XCHG

BC 536

Abstract: FRB CRS AN2491
Contextual Info: Freescale Semiconductor, Inc. Application Note AN2491 Rev. 0, 9/2003 Freescale Semiconductor, Inc. Simplified Mnemonics for PowerPC Instructions Jerry Young, NCSD Applications Simplified Mnemonics for PowerPC™ Instructions This document describes simplified mnemonics, which are provided for easier coding of

TMS320C54x, instruction set

Abstract: 00FF SMEM
Contextual Info: SPRZ118 Manual Update Sheet DATE: August 1, 1997 Document Being Updated: TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction Set Literature Number Being Updated: SPRU172 Manual Included in a Kit: Yes This Manual Update Sheet SPRZ118 ships with the TMS320C54x DSP Reference Set, Volume 2:

compal service manual

Abstract: M/1E54H 1E06H
Contextual Info: in tel. APPENDIX C REGISTERS This appendix provides reference information about the device registers. Table C-l lists the mod­ ules and major components of the device with their related configuration and status registers. Ta­ ble C-2 lists the registers, arranged alphabetically by mnemonic, along with their names,

PC15-8

Contextual Info: HIGH–SPEED MICROCONTROLLER USER’S GUIDE SECTION 16: INSTRUCTION SET DETAILS INSTRUCTION CODE ARIT ITHM METIC OP PERA ATION MNEMONIC HEX BYTE CYCLE EXPLANATION D7 D6 D5 D4 D3 D2 D1 D0 ADD A, Rn 1 1 n2 n1 n0 28-2F 1 1 A = (A) + (Rn) ADD A, direct a7 a6

FRB 914

Contextual Info: SECTION 9 INSTRUCTION SET This section describes individual instructions, including a description of instruction formats and notation and an alphabetical listing of RCPU instructions by mnemonic. 9.1 Instruction Formats Instructions are four bytes long and word-aligned, so when instruction addresses