MNA6 Search Results

Contextual Info: 74LVC1G14 Single Schmitt-trigger inverter Rev. 12 — 6 August 2012 Product data sheet 1. General description The 74LVC1G14 provides the inverting buffer function with Schmitt-trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free

nz104

Contextual Info: 74LVC2G66 Bilateral switch Rev. 7 — 22 June 2012 Product data sheet 1. General description The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each switch has two input/output terminals nY and nZ and an active HIGH enable input (nE).

application note tssop5 nxp

Contextual Info: 74LVC1G06 Inverter with open-drain output Rev. 10 — 29 June 2012 Product data sheet 1. General description The 74LVC1G06 provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

Contextual Info: 74LVC1G08 Single 2-input AND gate Rev. 9 — 9 December 2011 Product Specification 1. General description The 74LVC1G08 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.

MARKING V7 6-PIN

Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 11 — 6 July 2012 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

marking VU SOT363

Contextual Info: 74LVC1G11 Single 3-input AND gate Rev. 7 — 4 July 2012 Product data sheet 1. General description The 74LVC1G11 provides a single 3-input AND gate. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Contextual Info: 74LVC1GU04 Inverter Rev. 11 — 2 July 2012 Product data sheet 1. General description The 74LVC1GU04 provides the inverting single state unbuffered function. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

74LVC646A

Abstract: 74LVC646AD 74LVC646ADB 74LVC646APW SO24 SSOP24 TSSOP24
Contextual Info: 74LVC646A Octal bus transceiver/register; 3-state Rev. 04 — 29 June 2004 Product data sheet 1. General description The 74LVC646A is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

74AUP1G80

Abstract: 74AUP1G80GF 74AUP1G80GM 74AUP1G80GW MO-203
Contextual Info: 74AUP1G80 Low-power D-type flip-flop; positive-edge trigger Rev. 01 — 20 October 2006 Product data sheet 1. General description The 74AUP1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

74ABT821N

Abstract: 74ABT374A 74ABT534A 74ABT821 74ABT821D 74ABT821DB 74ABT821PW JESD78 SO24
Contextual Info: 74ABT821 10-bit D-type flip-flop; positive-edge trigger; 3-state Rev. 02 — 12 April 2005 Product data sheet 1. General description The 74ABT821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

74LVC1G53

Abstract: 74LVC1G53DC 74LVC1G53DP 74LVC1G53GD 74LVC1G53GT JESD22-A114E MO-187 V53 TSSOP8
Contextual Info: 74LVC1G53 2-channel analog multiplexer/demultiplexer Rev. 05 — 11 June 2008 Product data sheet 1. General description The 74LVC1G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device. The 74LVC1G53 provides one analog multiplexer/demultiplexer with a digital select

74ALVT16821

Abstract: 74ALVT16821DGG 74ALVT16821DL JESD78 SSOP56 TSSOP56 diode 1d8
Contextual Info: 74ALVT16821 20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state Rev. 03 — 13 June 2005 Product data sheet 1. General description The 74ALVT16821 high-performance Bipolar Complementary Metal Oxide Semiconductor BiCMOS device combines low static and dynamic power dissipation with

74LVC3G14

Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187
Contextual Info: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 07 — 12 June 2008 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger action. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

74LVC1G3157GV

Abstract: 74LVC1G3157GW 74LVC1G3157 74LVC1G3157GF 74LVC1G3157GM JESD22-A114E
Contextual Info: 74LVC1G3157 2-channel analog multiplexer/demultiplexer Rev. 02 — 18 September 2007 Product data sheet 1. General description The 74LVC1G3157 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC1G3157 provides one analog multiplexer/demultiplexer with one digital select

74LVC1G06

Abstract: 74LVC1G06GF 74LVC1G06GM 74LVC1G06GV 74LVC1G06GW JESD22-A114E
Contextual Info: 74LVC1G06 Inverter with open-drain output Rev. 07 — 12 July 2007 Product data sheet 1. General description The 74LVC1G06 provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

74LVC162244A

Abstract: 74LVC162244ADGG 74LVC162244ADL 74LVCH162244A 74LVCH162244ADGG 74LVCH162244ADL SSOP48
Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74LVC162244A; 74LVCH162244A 16-bit buffer/line driver, 30 Ω series termination resistors; 5 V tolerant input/output; 3-state Product specification Supersedes data of 1998 Feb 17 2003 Dec 12 Philips Semiconductors Product specification

74AUP1G126

Abstract: 74AUP1G126GF 74AUP1G126GM 74AUP1G126GW JESD22-A114-C MO-203
Contextual Info: 74AUP1G126 Low-power buffer/line driver; 3-state Rev. 02 — 28 June 2006 Product data sheet 1. General description The 74AUP1G126 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all

74LVC2G66

Abstract: 74LVC2G66DC 74LVC2G66DP 74LVC2G66GT 74LVCV2G66 JESD22-A114E JESD78
Contextual Info: 74LVC2G66 Bilateral switch Rev. 04 — 1 July 2008 Product data sheet 1. General description The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each switch has two input/output terminals nY and nZ and an active HIGH enable input (nE).

74LVC2G126

Abstract: 74LVC2G126DC 74LVC2G126DP 74LVC2G126GD 74LVC2G126GM 74LVC2G126GT JESD22-A114E MO-187
Contextual Info: 74LVC2G126 Dual bus buffer/line driver; 3-state Rev. 08 — 5 May 2008 Product data sheet 1. General description The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each 3-state output is controlled by an output enable input pin nOE . A LOW-level at pin nOE

74LVC4245A

Abstract: 74LVC4245ABQ 74LVC4245AD 74LVC4245ADB 74LVC4245APW JESD22-A114E SO24 SSOP24
Contextual Info: 74LVC4245A Octal dual supply translating transceiver; 3-state Rev. 06 — 18 January 2008 Product data sheet 1. General description The 74LVC4245A is an octal dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to

JESD22-A114E

Abstract: PDI1284P11 PDI1284P11DGG PDI1284P11DL SSOP48 TSSOP48
Contextual Info: PDI1284P11 3.3 V parallel interface transceiver/buffer Rev. 03 — 25 August 2008 Product data sheet 1. General description The PDI1284P11 parallel interface chip is designed to provide an asynchronous, 8-bit, bidirectional, parallel interface for personal computers. The PDI1284P11 includes all 19

74LVC2G241

Abstract: 74LVC2G241DC 74LVC2G241DP 74LVC2G241GD 74LVC2G241GM 74LVC2G241GT JESD22-A114E
Contextual Info: 74LVC2G241 Dual buffer/line driver; 3-state Rev. 09 — 10 June 2008 Product data sheet 1. General description The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE:

74LVC16241A

Abstract: 74LVC16241ADGG 74LVC16241ADL SSOP48 TSSOP48
Contextual Info: 74LVC16241A 16-bit buffer/line driver with 5 V tolerant inputs/outputs; 3-state Rev. 03 — 16 February 2004 Product data sheet 1. General description The 74LVC16241A is a high-performance, low-power and low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

74LV374

Abstract: 74HC374 74HCT374 74LV374D 74LV374N DIP20 JESD22-A114E SO20 SSOP20
Contextual Info: 74LV374 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 02 — 14 May 2009 Product data sheet 1. General description The 74LV374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input CP and an output enable