MAX921 Search Results

c485

Contextual Info: 19-3557; Rev 0; 2/05 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control

MAX9217

Abstract: MAX9218 MAX9218ECM MAX9218ETM
Contextual Info: 19-3557; Rev 2; 10/05 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control

Contextual Info: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

LVDS Serializer

Contextual Info: 27-BIT LVDS SERIALIZER/ DESERIALIZER LINK SYSTEMS WITH A SINGLE TWISTED-PAIR WIRE Ideal for LCDs Up to 480 x 800 Resolution ENHANCED ESD PROTECTION 18-BIT VIDEO DATA REDUCE COST BY ELIMINATING WIRES MAX9217 MAX9218 0.1µF 0.1µF PARALLEL OUTPUTS TO LCD DC BALANCE

DS90CR216A

Abstract: DS90CR218A MAX9210 MAX9215 MAX9222
Contextual Info: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

MAX9220EUM

Contextual Info: 19-2864; Rev 1; 10/03 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 feature programmable DC balance, which allows isolation between a serializer and deserializer using AC-coupling. A deserializer decodes data transmitted by a MAX9209/MAX9211/MAX9213/MAX9215

Nand gate Oscillator

Abstract: 5V-to-15V SCHMITT-TRIGGER AN110 APP110 MAX921 Comparator application note Boost Converter "quad comparator" application note
Contextual Info: Maxim > App Notes > Amplifier and comparator circuits Keywords: DC-DC converter, low load currents, boost converter, Schmitt-trigger NAND gate Jul 09, 1998 APPLICATION NOTE 110 Boost converter has high efficiency at light loads Abstract: This design note shows how a boost converter is designed from a quad Schmitt-trigger NAND gate and the MAX921, a

lcd 40 pin diagram lvds

Abstract: LVDS Serializer HSYNC, VSYNC input output MAX9217 MAX9217ECM MAX9217ETM MAX9218
Contextual Info: 19-3558; Rev 3; 5/08 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer The MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen bits of video data and 9 bits of control data are encoded and multiplexed onto the serial interface, reducing the serial data rate. The data enable input determines

UTP cat 6 cable

Contextual Info: 19-2828; Rev 5; 3/12 KIT ATION EVALU E L B A IL AVA Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides

MAX9217

Abstract: MAX9218 MAX9218ECM MAX9218ETM rgbout video in RGBout
Contextual Info: 19-3557; Rev 5; 8/09 KIT ATION EVALU E L B A AVAIL 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control

Contextual Info: 19-2864; Rev 5; 11/07 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9214/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing

MAX9217

Abstract: MAX9217ECM MAX9217ETM MAX9218
Contextual Info: 19-3558; Rev 4; 8/09 KIT ATION EVALU E L B A AVAIL 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer The MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen bits of video data and 9 bits of control data are

D4S20D-40ML5-Z

Abstract: h911 D4S20D H914 H918 H714 H710 LVTLL 13h3 GRM21BR61C106K
Contextual Info: 19-4939; Rev 0; 9/09 MAX9217/MAX9218 Evaluation Kit The MAX9217/MAX9218 evaluation kit EV kit provides a proven design to evaluate the MAX9217 27-bit, 3MHz to 35MHz DC-balanced LVDS serializer and the MAX9218 27-bit, 3MHz to 35MHz DC-balanced LVDS deserializer.

DS90CR215

Abstract: DS90CR217 MAX9209 MAX9209ETM MAX9209EUM MAX9209GUM MAX9213 marking code 56l MAX9213ETM
Contextual Info: 19-2828; Rev 4; 10/07 Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization.

MAX9217

Abstract: MAX9217ECM MAX9217ETM MAX9218 lcd cmf
Contextual Info: 19-3558; Rev 1; 4/05 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer Features The MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen bits of video data and 9 bits of control data are

MAX9217

Abstract: MAX9218 MAX9218ECM MAX9218ETM
Contextual Info: 19-3557; Rev 4; 5/08 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control

DS90CR215

Abstract: DS90CR217 MAX9209 MAX9209ETM MAX9209EUM MAX9209GUM MAX9213 marking aaa MAX9213ETM
Contextual Info: 19-2828; Rev 4; 10/07 KIT ATION EVALU E L B AVAILA Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides

Contextual Info: 19-2828; Rev 5; 3/12 KIT ATION EVALU E L B A IL AVA Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides

MAX9220EUM

Contextual Info: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

7x7x1.4

Abstract: T4866
Contextual Info: 19-3558; Rev 0; 2/05 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer Features The MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen bits of video data and 9 bits of control data are

DS90CR215

Abstract: DS90CR217 MAX9209 MAX9209ETM MAX9209EUM MAX9210 MAX9211 MAX9213ETM
Contextual Info: 19-2828; Rev 2; 2/04 Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9211/MAX9213/MAX9215 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization.

DS90CR215

Abstract: DS90CR217 MAX9209 MAX9210 MAX9211 MAX9213 MAX9215 marking aaa MAX9213ETM
Contextual Info: 19-2828; Rev 3; 6/07 Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9211/MAX9213/MAX9215 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization.

MAX9217

Abstract: MAX9217ECM MAX9217ETM MAX9218 rgb 18 bit to lvds LVDS Serializer
Contextual Info: 19-3558; Rev 2; 10/05 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer Features The MAX9217 digital video parallel-to-serial converter serializes 27 bits of parallel data into a serial data stream. Eighteen bits of video data and 9 bits of control data are

DS90CR216A

Abstract: DS90CR218A MAX9210ETM MAX9210EUM MAX9212ETM
Contextual Info: 19-2864; Rev 0; 4/03 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216 feature programmable DC balance, which allows isolation between serializer and deserializer using AC-coupling. A deserializer decodes data transmitted by a