LVTLL Search Results

SO-DIMM 100-pin

Abstract: A839 NC133 SL936512K2M-09DFVG SO-DIMM 144-pin
Contextual Info: Advanced* SL936512K2M-09DFVG 512K X 36 Bits 2MB Flow-Through Synchronous SRAM 144-Pin SO-DIMM FEATURES GENERAL DESCRIPTION • Performance range: 8.5ns up to 87MHz clock frequency • • • • +3.3V + 0.3V power supply Byte write capability LVTLL compatible inputs and outputs

Contextual Info: INTEGRATED CIRCUITS GTL2005 Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator Product specification Supersedes data of 1999 Jun 23 Philips Semiconductors 1999 Sep 17 Philips Semiconductors Product specification Quad GTL/GTL+ to LVTLL/TTL bidirectional non-latched translator

of TX6A RX6A

Abstract: RX6A tx2c transmitter RX6a 1211 TX1B TXC-06885 diode GFP AA tx6c TX5b rx5b Ethernet over SONET mapper
Contextual Info: Envoy -CE4 Device SPI-3 to Ethernet Controller TXC-06885 DATA SHEET PRODUCT PREVIEW • 4 Configurable Media Access Controllers MACs • Each MAC is configurable as 8 Fast Ethernet ports (10/100 Mbits/s) or 2 Fast Ethernet ports with extended buffers or 1 Gigabit Ethernet port (10/100/1000 Mbits/s)

Contextual Info: 4M x 32 -Bit EDO-DRAM Module SMALL OUTLINE MEMORY MODULE HYM32 V4025G D-50/-60 HYM32V4025GDL-50/-60 Advanced Information • 72-Pin Small Outline Dual-in-Line Memory Module • 4 194 034 words by 32-bit organization • Hyper Page Mode - EDO - performance

L-DIM-72-3

Contextual Info: 4M x 32 -Bit Dynamic RAM Module SMALL OUTLINE MEMORY MODULE HYM 32V4020G D L -50/-60 Advanced Information • 72-Pin Small Outline Dual-in-Line Memory Module • 4 194 034 words by 32-bit organization • Performance: -50 -60 Read / Write Cycle Time 90 110

Contextual Info: FPD-Link Evaluation Kit User Manual FPD-Link Demonstration Kit User Manual P/N: FLINK3V10BT-TX/RX Rev 0.6 Flat Panel Displays National Semiconductor Corporation Flat Panel Displays LIT# FLINK3V10BT-TX/RX -UM Rev 0.6 5/16/2008 Page 1 of 40 FPD-Link Evaluation Kit User Manual

Contextual Info: D S90C 3201 DS90C3201 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter T ex a s In s t r u m e n t s Literature Number: SNLS192C Semiconductor DS90C3201 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter General Description Features The DS90C3201 is a 3.3V single/dual FPD-Link 10-bit color

app abstract

Abstract: SN74FB2041A
Contextual Info: TSB14AA1A, TSB14AA1AI, TSB14AA1AT 3.3ĆV IEEE 1394-1995 Backplane PHY Data Manual April 2003 MSDS1394 SLLS465D IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue

LVCMOS25

Abstract: LVCMOS15 LVCMOS33 LVCMOS18 ECP2M date sheet of ninth class
Contextual Info: LatticeECP2/M sysIO Usage Guide June 2010 Technical Note TN1102 Introduction The LatticeECP2 and LatticeECP2M™ sysIO™ buffers give the designer the ability to easily interface with other devices using advanced system I/O standards. This technical note describes the sysIO standards available and

LC4064ZE

Abstract: BSDL Files infineon LFXP6C-3FN256I "x-ray machine" K4H560838E LC4064 LC4256ZE LFXP10C-3F256I LFxP3C-3TN144C PCI x1 express PCB dimensions artwork
Contextual Info: LatticeXP Family Handbook HB1001 Version 03.4, September 2010 LatticeXP Family Handbook Table of Contents September 2010 Section I. LatticeXP Family Data Sheet Introduction Features . 1-1

verilog code for mdio protocol

Abstract: AMBA AHB to APB BUS Bridge verilog code amba apb verilog coding RTL code for ethernet W32 MARKING AA13 AA15 MAC110 QL901M verilog coding for APB bridge
Contextual Info: QL901M QuickMIPS Data Sheet • • • • • • QuickMIPS ESP Family 1.0 Overview The QuickMIPS™ Embedded Standard Products ESPs family provides an out-of-the box solution consisting of the QL901M QuickMIPS chip and the QuickMIPS development environment. The

LCK4973

Abstract: 2336 a
Contextual Info: a8e re AdLib OCR Evaluation systems Preliminary Data Sheet November 2002 LCK4973 Low-Voltage PLL Clock Driver Features Description . Fully integrated PLL . Agere Systems' LCK4973 is a 3.3 V12.5 V, PLL-based clock driver for high-performance RISC or CISC processor-based systems. The LCK4973 has

1kx4

Abstract: ALTERA MAX 3000 Altera MAX V CPLD PQFP ALTERA 160 Q302 EP1C12 altera TQFP 32 PACKAGE altera cyclone 3 F324 Altera
Contextual Info: Семейство Cyclone Copyright 2003 Altera Corporation 1 Семейства микросхем Altera „ Семейства программируемой логики – FPGA высокой и средней степени интеграции;

IDTQS32XVH2245

Abstract: QS32XVH2245 32XVH2245
Contextual Info: IDTQS32XVH2245 3.3V 16-BIT BUS SWITCH FOR HOT SWAP APPLICATIONS INDUSTRIAL TEMPERATURE RANGE QUICKSWITCH PRODUCTS 3.3V 16-BIT BUS SWITCH FOR HOT SWAP APPLICATIONS HOTSWITCH IDTQS32XVH2245 FEATURES: DESCRIPTION: − The QS32XVH2245 HotSwitch 16-bit bus switch is specially designed for

cal 3200

Abstract: fec 34 IT 238 GR-1244-CORE OC192 Si5320 Si5320-X-BC
Contextual Info: Si5320 SONET/SDH P R E C I S I O N C L O C K M U L T I P L I E R I C Features „ Ultra-low-jitter clock output with jitter generation as low as 0.3 psRMS „ „ No external components other than a resistor and standard bypassing „ Input clock ranges at 19, 39, 78,

UPD 056

Abstract: CBAW
Contextual Info: ASPEN Express Device DATA SHEET PRODUCT PREVIEW FEATURES DESCRIPTION The ASPEN Express device is a single-chip solution for implementing cost-effective ATM multiplexing and switching systems, based on the CellBus architecture. Such systems are constructed from a number of CUBIT-3, CUBIT-Pro,

Contextual Info: LatticeECP/EC Family Handbook HB1000 Version 03.7, September 2012 LatticeECP/EC Family Handbook Table of Contents September 2012 Section I. LatticeECP/EC Family Data Sheet Introduction Features . 1-1

AD6555

Abstract: GSM based home appliance control circuit diagram mp3 player circuit diagram by using msp430 microprocessor coffee vending machine ADSP-BF525 ADSP-21160 ADSP-21161N ADSP-21262 ADSP-21266 ADSP-TS203S
Contextual Info: Embedded Processors and DSP Selection Guide 2007 Edition www.analog.com/processors Obtaining Information HOW TO OBTAIN INFORMATION FROM ANALOG DEVICES Europe and Israel Analog Devices publishes data sheets and a host of other technical literature supporting our products and technologies. Follow the

msop5

Abstract: VT150 B14 diode on semiconductor
Contextual Info: Envoy -8FE Device Octal Fast Ethernet Controller TXC-06840 DATA SHEET NETWORK SIDE +1.8v +3.3v 10/100 Mbit/s SMII Port 0 10/100 Mbit/s SMII (Port 7) z z z z z z U.S. and/or foreign patents issued or pending Copyright 2003 TranSwitch Corporation Envoy is a trademark of TranSwitch Corporation

ST40 manual

Abstract: JTAG STi5514 0x1ff0000 ST40-STB1 aseram 0x1B01FFFF ST40STB1 sh4 stmicroelectronics ST40 System Architecture - Volume 4 I/O Devices
Contextual Info: ST40RA166 32-bit Embedded SuperH Device PRELIMINARY DATA Integer & FP Execution Units 24 Data JTAG JTAG Debug PIO Interface Registers UDI SCIF MMU D Cache MMU I Cache SCIF 5 Channel DMA Controller Timer TMU Real Time Clk Cbus Bridge/ SuperHyway I/F 2 Channel

2114 1k x 4 SRAM

Abstract: AGLN010
Contextual Info: Advance v0.2 IGLOO nano Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Advanced I/Os • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS

DS90CR482

Abstract: DS90CR483 DS90CR484 DS90CR485 DS90CR486 PRBS-15 termination sense
Contextual Info: DS90CR485 133MHz 48-bit Channel Link Serializer 6.384 Gbps General Description The DS90CR485 serializes the 24 LVCMOS/LVTTL double edge inputs (48 bits data latched in per clock cycle) onto 8 Low Voltage Differential Signaling (LVDS) streams. A phaselocked transmit clock is also in parallel with the data streams

AD2813

Abstract: ADN2813 AN-632 GR-253-CORE ad281
Contextual Info: Continuous Rate 12.3 Mb/s to 1.25 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2813 Preliminary Technical Data FEATURES PRODUCT DESCRIPTION Serial data input: 12.3 Mb/s to 1.25 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance

Contextual Info: IGLOO nano Handbook IGLOO nano Handbook Table of Contents Low-Power Flash Device Handbooks Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Section I – IGLOO nano Datasheet IGLOO nano Low-Power Flash FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I