MAX9222 Search Results

Contextual Info: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

DS90CR216A

Abstract: DS90CR218A MAX9210 MAX9215 MAX9222
Contextual Info: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

MAX9220EUM

Contextual Info: 19-2864; Rev 1; 10/03 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 feature programmable DC balance, which allows isolation between a serializer and deserializer using AC-coupling. A deserializer decodes data transmitted by a MAX9209/MAX9211/MAX9213/MAX9215

Contextual Info: 19-2864; Rev 5; 11/07 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9214/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing

MAX9220EUM

Contextual Info: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

MAX9220EUM

Contextual Info: MAX9210/MAX9214/ MAX9220/MAX9222 General Description The MAX9210/MAX9214/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply,

EPS17

Abstract: MAX9220EUM
Contextual Info: 19-2864; Rev 1; 10/03 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 feature programmable DC balance, which allows isolation between a serializer and deserializer using AC-coupling. A deserializer decodes data transmitted by a MAX9209/MAX9211/MAX9213/MAX9215

MAX9210

Abstract: MAX9215 MAX9222 DS90CR216A DS90CR218A MAX9220EUM
Contextual Info: 19-2864; Rev 3; 4/04 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

DS90CR216A

Abstract: DS90CR218A MAX9210 MAX9222 MAX9220EUM
Contextual Info: 19-2864; Rev 1; 8/03 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 feature programmable DC balance, which allows isolation between a serializer and deserializer using AC-coupling. A deserializer decodes data transmitted by a MAX9209/MAX9211/MAX9213/MAX9215

DS90CR216A

Abstract: DS90CR218A MAX9210EUM
Contextual Info: 19-2864; Rev 5; 11/07 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9214/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing

Contextual Info: 19-3641; Rev 1; 10/07 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for

aec-q100

Abstract: AEC-Q100-011 G700K TSMC 1P4M MAX1782ETM tsmc cmos 0.11 um tsmc cmos model AC07X-1Z AB8200T MAX1782
Contextual Info: Automotive Qualification Report MAX7042ATJ+ 308MHz/315MHz/ 418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver Grade 1 32-Lead TQFN 5 x 5 mm AEC-Q100 Rev. F Tests MSL 1 - Preconditioning PC Biased HAST (HAST) 9 9 9 Lot # 2 (Q43ACQ001B) MAX1499EHJ Maxim

AN3821

Abstract: MAX9209 MAX9214 MAX9222 MAX9238 MAX9242 MAX9244 MAX9246
Contextual Info: Maxim > App Notes > AUTOMOTIVE CLOCK GENERATION AND DISTRIBUTION HIGH-SPEED SIGNAL PROCESSING MISCELLANEOUS CIRCUITS HIGH-SPEED INTERCONNECT Keywords: 21-bit multiple input channel deserializers, skew margin measurement, jitter tolerance, clock jitter, data

max9234

Abstract: MAX9234EUM MAX9236EUM MAX9238
Contextual Info: 19-3641; Rev 0; 4/05 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for

Contextual Info: MAX9234/MAX9236/ MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers General Description The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for

Contextual Info: 19-3641; Rev 0; 4/05 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for

Contextual Info: MAX9234/MAX9236/ MAX9238 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers General Description The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for

Contextual Info: 19-3641; Rev 0; 4/05 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for

max9234eum

Abstract: MAX9234 MAX9236EUM MAX9238 marking aaa
Contextual Info: 19-3641; Rev 1; 10/07 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for