M74LS Search Results

m74LS164p

Abstract: CRB 400P IC dsi 20-PIN RD 15 mitsubishi
Contextual Info: MITSUBISHI LSTTLs M74LS164P 8 -B IT SER IA L-IN PARALLEL-OUT S H IFT REGISTER DESCRIPTION The M 74LS 164P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing an 8 -b it serial input-serial/parallel ou tp ut shift register fu nction w ith direct reset input.

semiconductor w5c

Abstract: 20-PIN 251C M74LS395AP
Contextual Info: MITSUBISHI LSTTLs M74LS395AP 4 -B IT CASCADABLE S H IFT REG ISTER W IT H 3-S TA TE O UTPUT DESCRIPTION T h e M 7 4 L S 3 9 5 A P is a s em ico n d u c to r in teg ra te d c irc u it PIN CONFIGURATION TOP VIEW co n ta in in g a 3-state o u tp u t 4 -b it s e rial/p a ralle l in p u t-s e ria l/

M74LS156P

Abstract: 20-PIN M74LS155P
Contextual Info: MITSUBISHI LSTTLs M74LS156P DUAL 2 -B IT BINARY TO 4-LINE DECODER/DEMULTIPLEXER W ITH OPEN COLLECTOR OUTPUT DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74L S 15 6P is containing tw o a semiconductor integrated circuit 2-bit binary to 4-line decoders/dem ulti­

20-PIN

Abstract: 50J2 M74LS386P
Contextual Info: MITSUBISHI LSTTLs M74LS386P QUADRUPLE 2-IN P U T EXCLUSIVE OR GATE DESCRIPTION The M 7 4 L S 3 8 6 P is a semiconductor circuit containing four integral circuits configured into dual input exclusive OR gates. FEATURES • Capable o f withstanding high input voltages V , ^ 1 5 V

M74LS643-1P

Abstract: M74LS643P
Contextual Info: M ITSUBISHI L S T T L s M74LS643P O C TA L B U S T R A N S C E IV E R W ITH 3 -S T A T E O U TP U T D ES C R IP TIO N The M 7 4 LS6 4 3 P is a sem iconductor integrated circuit con­ taining 8 bus transmitter/receiver circuits with inverted and non-inverted outputs.

M74LS640-1P

Abstract: 20P4 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS640-1P OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M 74L S 64 0-1P is a semiconductor integrated circuit containing 8 bus transmitters/receivers w ith inverted ou t­ puts. DATA

BCD-TO-7-SEGMENT DECODER

Abstract: m74ls248p M74LS247P M74LS48P m74ls48 M74LS47P
Contextual Info: MITSUBISHI LSTTLs M74LS248P B C D -TO -7 -SEGM ENT D EC O D ER /D R IVER A C TIV E -H IG H O U TP U T DESCRIPTION The M 7 4L S 24 8P is a semiconductor integrated circuit pro­ vided w ith a BCD-to-7-segment decoder/driver function and 2kohm (typ ) pull-up resistor outputs.

M74LS138P

Abstract: M74LS137P 20-PIN demultiplexer containing latch 1329T
Contextual Info: MITSUBISHI LSTTLs M74LS137P 3-LINE-TO -8-LINE DECODER/DEMULTIPLEXER W ITH ADDRESS LATCH DESCRIPTION The M 7 4L S 13 7P is a semiconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW taining a 3-line-to-8-line decoder/m ultiplexer function w ith address latch.

20-PIN

Abstract: M74LS670P
Contextual Info: MITSUBISHI LSTTLs M74LS670P 4 -B Y -4 REGISTER FILE W ITH 3-STATE OUTPUTS DESCRIPTION PIN CONFIGURATION TOP VIEW The M74LS670P is a semiconductor integrated circuit containing a 4 word x 4 bit register file circuit with 3-state outputs. i Di — [7 16] V cc

M74LS540P

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS540P OCTAL BUFFER/LINE DRIVER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION The M 74L S 54 0P PIN CONFIGURATION (TOP VIEW) is a semiconductor integrated circuit _ O UTPUT containing 1 block o f buffer w ith 3-state inverted output

M74LS247P

Abstract: 7 segment 4" LT display M74LS47P 4 digits 7-segment led display display 7 segment smd 4 digits 7-segment display cl BCD-TO-7-SEGMENT DECODER 4 digits 7-segment led display cl BCD-TO-7-SEGMENT 7 segment 4 LT display
Contextual Info: MITSUBISHI LSTTLs M74LS247P B C D -TO -7-S EG M E N T D E C O D E R /D R IV E R A C T IV E -L O W O U TP U T DESCRIPTION The M74LS247P is a semiconductor integrated circuit PIN CONFIGURATION (TOP VIEW) provided with BCD-to-7-segment decoder/driver function

20-PIN

Abstract: M74LS298P M74LS298
Contextual Info: MITSUBISHI LS TT Ls M 74LS298P QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE DESCRIPTION The M74LS298P is a sem iconductor integrated circuit PIN CONFIGURATION TOP VIEW which containing fo u r 2-line to 1-line m ultiplexers provided w ith a tem porary storage circu it w ith common selection

mitsubishi inverter schematic

Abstract: mitsubishi inverter air conditioning M74LS19P M74ls14p 20-PIN 74LS14P
Contextual Info: MITSUBISHI LSTTLs M74LS19P H EX SCH M ITT TRIGGER INVERTER DESCRIPTION T h e M 7 4 L S 1 9 P is a s em ico n d u c to r in teg rated c irc u it c o n ­ ta in in g 6 s c h m itt trigg er in ve rte r circuits. FEATURES • S u ita b le fo r w a v e fo rm shaping applications

M74LS166AP

Abstract: 50J2 M74LS166P 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS166AP 8 -B IT SH IFT REGISTER DESCRIPTION The M 7 4L S 16 6A P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW containing an 8-bit serial/parallel input — serial ou tp u t shift register function. S E R IA L DATA

M74LS92P

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS92P DIVIDE-BY-TW ELVE COUNTER DESCRIPTION The M74LS92P is a semiconductor integrated circuit containing an asynchronous divide-by-twelve counter func­ tion w ith direct reset inputs. FEATURES • • • • Direct reset input provided

m74ls194ap

Abstract: 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS194AP 4 -B IT B ID IR E C TIO N A L U N IV ER SA L S H IF T REG ISTER W IT H RESET DESCRIPTION The M 7 4L S 19 4A P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW w ith a 4-b it bidirectional serial/parallel input-serial/parallel

50J2

Abstract: LS290 LS90 M74LS490P
Contextual Info: MITSUBISHI LSTTLs M74LS490P DUAL 4 -B IT DECADE COUNTER DESCRIPTION The M74LS490P is a semiconductor integrated circuit containing a dual circuit asynchronous decade counter with direct reset input and direct 9-set input. FEATURES • Two integral circuits the functional equivalent of LS90

M74LS11P

Abstract: 20-PIN M74LS11
Contextual Info: MITSUBISHI LSTTLs M74LS11P TR IP LE 3 -IN P U T P O S ITIV E AND GATE DESCRIPTION The M 74LS11P is a s e m ico n d u c to r in teg rated c irc u it PIN CONFIGURATION TOP VIEW c o n ta in in g th re e tr ip le -in p u t positive A N D and negative O R gates.

M74LS38P

Abstract: mitsubishi air conditioning 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS38P Q U AD R UPLE 2 -IN P U T P O S IT IV E NAND BUFFER W IT H OPEN COLLECTOR OUTPU T DESCRIPTION PIN CONFIGURATION TOP VIEW The M74LS38P is a semiconductor integrated circu it containing fo u r 2-input positive N AN D and negative NOR

M74LS12P

Abstract: 74LS12P 20-PIN
Contextual Info: MITSUBISHI LSTTLs M 7 4 LS1 2 P T R IP L E 3-INPUT P O SITIV E NAND GATE WITH OPEN CO LLECTO R OUTPUT DESCRIPTION The M74LS12P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing three triple-input positive-logic NAND gates with open collector outputs, usable as negative-logic NOR

Contextual Info: MITSUBISHI LSTTLs M74LS367AP H EX BUS D R IVER S W IT H 3 -S T A T E O UTPU TS DESCRIPTION The M 7 4L S 36 7A P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW constaining 6 buffers w ith 3-state ou tp ut and is provided w ith ou tp u t control

M74LS27P

Contextual Info: MITSUBISHI LSTTLs M74LS27P TRIPLE 3-INPUT POSITIVE NOR GATE DESCRIPTION The M74LS27P is a semiconductor PIN CONFIGURATION TOP VIEW integrated circu it containing three trip le -in p u t positive NOR and negative NAN D gates. “ W FEATURES IB • High breakdown in p u t voltage (V| ^ 15V)

Contextual Info: MITSUBISHI LS T T Ls M74LS353P DUAL 4-LIN E TO 1-LINE DATA SELECTOR/MULTIPLEXER W ITH 3-STATE OUTPUT INVERTED DESCRIPTION The M 74LS 353P is a semiconductor integrated circuit PIN CONFIGURATION (TOP VIEW) containing tw o 4-line to 1-line data selector/m ultiplexer

M74LS123P

Abstract: 74LS4 m74ls123
Contextual Info: MITSUBISHI LSTTLs M 74LS423P DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR W ITH RESET DESCRIPTION The PIN CONFIGURATION TOP VIEW M74LS423P is a semiconductor integrated c irc u it containing tw o retriggerable monostable m u ltivib ra to r cir­ cuits w ith direct reset inputs.